mcxa_pac/sgi0/
sgi_auto_dma_ctrl.rs

1#[doc = "Register `sgi_auto_dma_ctrl` reader"]
2pub type R = crate::R<SgiAutoDmaCtrlSpec>;
3#[doc = "Register `sgi_auto_dma_ctrl` writer"]
4pub type W = crate::W<SgiAutoDmaCtrlSpec>;
5#[doc = "Field `ife` reader - Input FIFO DMA Enable"]
6pub type IfeR = crate::BitReader;
7#[doc = "Field `ife` writer - Input FIFO DMA Enable"]
8pub type IfeW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `auto_dma_rsvd1` reader - reserved"]
10pub type AutoDmaRsvd1R = crate::FieldReader;
11#[doc = "Field `ofe` reader - Ouput FIFO DMA Enable"]
12pub type OfeR = crate::BitReader;
13#[doc = "Field `ofe` writer - Ouput FIFO DMA Enable"]
14pub type OfeW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `auto_dma_rsvd2` reader - reserved"]
16pub type AutoDmaRsvd2R = crate::FieldReader<u32>;
17impl R {
18    #[doc = "Bit 0 - Input FIFO DMA Enable"]
19    #[inline(always)]
20    pub fn ife(&self) -> IfeR {
21        IfeR::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bits 1:7 - reserved"]
24    #[inline(always)]
25    pub fn auto_dma_rsvd1(&self) -> AutoDmaRsvd1R {
26        AutoDmaRsvd1R::new(((self.bits >> 1) & 0x7f) as u8)
27    }
28    #[doc = "Bit 8 - Ouput FIFO DMA Enable"]
29    #[inline(always)]
30    pub fn ofe(&self) -> OfeR {
31        OfeR::new(((self.bits >> 8) & 1) != 0)
32    }
33    #[doc = "Bits 9:31 - reserved"]
34    #[inline(always)]
35    pub fn auto_dma_rsvd2(&self) -> AutoDmaRsvd2R {
36        AutoDmaRsvd2R::new((self.bits >> 9) & 0x007f_ffff)
37    }
38}
39#[cfg(feature = "debug")]
40impl core::fmt::Debug for R {
41    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
42        f.debug_struct("sgi_auto_dma_ctrl")
43            .field("ife", &self.ife())
44            .field("auto_dma_rsvd1", &self.auto_dma_rsvd1())
45            .field("ofe", &self.ofe())
46            .field("auto_dma_rsvd2", &self.auto_dma_rsvd2())
47            .finish()
48    }
49}
50impl W {
51    #[doc = "Bit 0 - Input FIFO DMA Enable"]
52    #[inline(always)]
53    pub fn ife(&mut self) -> IfeW<'_, SgiAutoDmaCtrlSpec> {
54        IfeW::new(self, 0)
55    }
56    #[doc = "Bit 8 - Ouput FIFO DMA Enable"]
57    #[inline(always)]
58    pub fn ofe(&mut self) -> OfeW<'_, SgiAutoDmaCtrlSpec> {
59        OfeW::new(self, 8)
60    }
61}
62#[doc = "SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_dma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_dma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
63pub struct SgiAutoDmaCtrlSpec;
64impl crate::RegisterSpec for SgiAutoDmaCtrlSpec {
65    type Ux = u32;
66}
67#[doc = "`read()` method returns [`sgi_auto_dma_ctrl::R`](R) reader structure"]
68impl crate::Readable for SgiAutoDmaCtrlSpec {}
69#[doc = "`write(|w| ..)` method takes [`sgi_auto_dma_ctrl::W`](W) writer structure"]
70impl crate::Writable for SgiAutoDmaCtrlSpec {
71    type Safety = crate::Unsafe;
72}
73#[doc = "`reset()` method sets sgi_auto_dma_ctrl to value 0"]
74impl crate::Resettable for SgiAutoDmaCtrlSpec {}
mcxa_pac/sgi0/sgi_auto_dma_ctrl.rs

mcxa_pac/sgi0/
sgi_auto_dma_ctrl.rs
