mcxa_pac/scg0/
spllsscg1.rs

1#[doc = "Register `SPLLSSCG1` reader"]
2pub type R = crate::R<Spllsscg1Spec>;
3#[doc = "Register `SPLLSSCG1` writer"]
4pub type W = crate::W<Spllsscg1Spec>;
5#[doc = "Field `SS_MDIV_MSB` reader - SS_MDIV\\[32\\]"]
6pub type SsMdivMsbR = crate::BitReader;
7#[doc = "Field `SS_MDIV_MSB` writer - SS_MDIV\\[32\\]"]
8pub type SsMdivMsbW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "SS_MDIV\\[32:0\\] change request.\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum SsMdivReq {
13    #[doc = "0: SS_MDIV change is not requested"]
14    Disabled = 0,
15    #[doc = "1: SS_MDIV change is requested"]
16    Enabled = 1,
17}
18impl From<SsMdivReq> for bool {
19    #[inline(always)]
20    fn from(variant: SsMdivReq) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `SS_MDIV_REQ` reader - SS_MDIV\\[32:0\\] change request."]
25pub type SsMdivReqR = crate::BitReader<SsMdivReq>;
26impl SsMdivReqR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> SsMdivReq {
30        match self.bits {
31            false => SsMdivReq::Disabled,
32            true => SsMdivReq::Enabled,
33        }
34    }
35    #[doc = "SS_MDIV change is not requested"]
36    #[inline(always)]
37    pub fn is_disabled(&self) -> bool {
38        *self == SsMdivReq::Disabled
39    }
40    #[doc = "SS_MDIV change is requested"]
41    #[inline(always)]
42    pub fn is_enabled(&self) -> bool {
43        *self == SsMdivReq::Enabled
44    }
45}
46#[doc = "Field `SS_MDIV_REQ` writer - SS_MDIV\\[32:0\\] change request."]
47pub type SsMdivReqW<'a, REG> = crate::BitWriter<'a, REG, SsMdivReq>;
48impl<'a, REG> SsMdivReqW<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "SS_MDIV change is not requested"]
53    #[inline(always)]
54    pub fn disabled(self) -> &'a mut crate::W<REG> {
55        self.variant(SsMdivReq::Disabled)
56    }
57    #[doc = "SS_MDIV change is requested"]
58    #[inline(always)]
59    pub fn enabled(self) -> &'a mut crate::W<REG> {
60        self.variant(SsMdivReq::Enabled)
61    }
62}
63#[doc = "Field `MF` reader - Modulation Frequency Control"]
64pub type MfR = crate::FieldReader;
65#[doc = "Field `MF` writer - Modulation Frequency Control"]
66pub type MfW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
67#[doc = "Field `MR` reader - Modulation Depth Control"]
68pub type MrR = crate::FieldReader;
69#[doc = "Field `MR` writer - Modulation Depth Control"]
70pub type MrW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
71#[doc = "Field `MC` reader - Modulation Waveform Control"]
72pub type McR = crate::FieldReader;
73#[doc = "Field `MC` writer - Modulation Waveform Control"]
74pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
75#[doc = "Dither Enable\n\nValue on reset: 0"]
76#[cfg_attr(feature = "defmt", derive(defmt::Format))]
77#[derive(Clone, Copy, Debug, PartialEq, Eq)]
78pub enum Dither {
79    #[doc = "0: Dither is not enabled"]
80    Disabled = 0,
81    #[doc = "1: Dither is enabled"]
82    Enabled = 1,
83}
84impl From<Dither> for bool {
85    #[inline(always)]
86    fn from(variant: Dither) -> Self {
87        variant as u8 != 0
88    }
89}
90#[doc = "Field `DITHER` reader - Dither Enable"]
91pub type DitherR = crate::BitReader<Dither>;
92impl DitherR {
93    #[doc = "Get enumerated values variant"]
94    #[inline(always)]
95    pub const fn variant(&self) -> Dither {
96        match self.bits {
97            false => Dither::Disabled,
98            true => Dither::Enabled,
99        }
100    }
101    #[doc = "Dither is not enabled"]
102    #[inline(always)]
103    pub fn is_disabled(&self) -> bool {
104        *self == Dither::Disabled
105    }
106    #[doc = "Dither is enabled"]
107    #[inline(always)]
108    pub fn is_enabled(&self) -> bool {
109        *self == Dither::Enabled
110    }
111}
112#[doc = "Field `DITHER` writer - Dither Enable"]
113pub type DitherW<'a, REG> = crate::BitWriter<'a, REG, Dither>;
114impl<'a, REG> DitherW<'a, REG>
115where
116    REG: crate::Writable + crate::RegisterSpec,
117{
118    #[doc = "Dither is not enabled"]
119    #[inline(always)]
120    pub fn disabled(self) -> &'a mut crate::W<REG> {
121        self.variant(Dither::Disabled)
122    }
123    #[doc = "Dither is enabled"]
124    #[inline(always)]
125    pub fn enabled(self) -> &'a mut crate::W<REG> {
126        self.variant(Dither::Enabled)
127    }
128}
129#[doc = "SS_MDIV select.\n\nValue on reset: 0"]
130#[cfg_attr(feature = "defmt", derive(defmt::Format))]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132pub enum SelSsMdiv {
133    #[doc = "0: Feedback divider ratio is MDIV\\[15:0\\]"]
134    Disabled = 0,
135    #[doc = "1: Feedback divider ratio is SS_MDIV\\[32:0\\]"]
136    Enabled = 1,
137}
138impl From<SelSsMdiv> for bool {
139    #[inline(always)]
140    fn from(variant: SelSsMdiv) -> Self {
141        variant as u8 != 0
142    }
143}
144#[doc = "Field `SEL_SS_MDIV` reader - SS_MDIV select."]
145pub type SelSsMdivR = crate::BitReader<SelSsMdiv>;
146impl SelSsMdivR {
147    #[doc = "Get enumerated values variant"]
148    #[inline(always)]
149    pub const fn variant(&self) -> SelSsMdiv {
150        match self.bits {
151            false => SelSsMdiv::Disabled,
152            true => SelSsMdiv::Enabled,
153        }
154    }
155    #[doc = "Feedback divider ratio is MDIV\\[15:0\\]"]
156    #[inline(always)]
157    pub fn is_disabled(&self) -> bool {
158        *self == SelSsMdiv::Disabled
159    }
160    #[doc = "Feedback divider ratio is SS_MDIV\\[32:0\\]"]
161    #[inline(always)]
162    pub fn is_enabled(&self) -> bool {
163        *self == SelSsMdiv::Enabled
164    }
165}
166#[doc = "Field `SEL_SS_MDIV` writer - SS_MDIV select."]
167pub type SelSsMdivW<'a, REG> = crate::BitWriter<'a, REG, SelSsMdiv>;
168impl<'a, REG> SelSsMdivW<'a, REG>
169where
170    REG: crate::Writable + crate::RegisterSpec,
171{
172    #[doc = "Feedback divider ratio is MDIV\\[15:0\\]"]
173    #[inline(always)]
174    pub fn disabled(self) -> &'a mut crate::W<REG> {
175        self.variant(SelSsMdiv::Disabled)
176    }
177    #[doc = "Feedback divider ratio is SS_MDIV\\[32:0\\]"]
178    #[inline(always)]
179    pub fn enabled(self) -> &'a mut crate::W<REG> {
180        self.variant(SelSsMdiv::Enabled)
181    }
182}
183#[doc = "SSCG Power Down\n\nValue on reset: 1"]
184#[cfg_attr(feature = "defmt", derive(defmt::Format))]
185#[derive(Clone, Copy, Debug, PartialEq, Eq)]
186pub enum SsPd {
187    #[doc = "0: SSCG is powered on"]
188    Disabled = 0,
189    #[doc = "1: SSCG is powered off"]
190    Enabled = 1,
191}
192impl From<SsPd> for bool {
193    #[inline(always)]
194    fn from(variant: SsPd) -> Self {
195        variant as u8 != 0
196    }
197}
198#[doc = "Field `SS_PD` reader - SSCG Power Down"]
199pub type SsPdR = crate::BitReader<SsPd>;
200impl SsPdR {
201    #[doc = "Get enumerated values variant"]
202    #[inline(always)]
203    pub const fn variant(&self) -> SsPd {
204        match self.bits {
205            false => SsPd::Disabled,
206            true => SsPd::Enabled,
207        }
208    }
209    #[doc = "SSCG is powered on"]
210    #[inline(always)]
211    pub fn is_disabled(&self) -> bool {
212        *self == SsPd::Disabled
213    }
214    #[doc = "SSCG is powered off"]
215    #[inline(always)]
216    pub fn is_enabled(&self) -> bool {
217        *self == SsPd::Enabled
218    }
219}
220#[doc = "Field `SS_PD` writer - SSCG Power Down"]
221pub type SsPdW<'a, REG> = crate::BitWriter<'a, REG, SsPd>;
222impl<'a, REG> SsPdW<'a, REG>
223where
224    REG: crate::Writable + crate::RegisterSpec,
225{
226    #[doc = "SSCG is powered on"]
227    #[inline(always)]
228    pub fn disabled(self) -> &'a mut crate::W<REG> {
229        self.variant(SsPd::Disabled)
230    }
231    #[doc = "SSCG is powered off"]
232    #[inline(always)]
233    pub fn enabled(self) -> &'a mut crate::W<REG> {
234        self.variant(SsPd::Enabled)
235    }
236}
237impl R {
238    #[doc = "Bit 0 - SS_MDIV\\[32\\]"]
239    #[inline(always)]
240    pub fn ss_mdiv_msb(&self) -> SsMdivMsbR {
241        SsMdivMsbR::new((self.bits & 1) != 0)
242    }
243    #[doc = "Bit 1 - SS_MDIV\\[32:0\\] change request."]
244    #[inline(always)]
245    pub fn ss_mdiv_req(&self) -> SsMdivReqR {
246        SsMdivReqR::new(((self.bits >> 1) & 1) != 0)
247    }
248    #[doc = "Bits 2:4 - Modulation Frequency Control"]
249    #[inline(always)]
250    pub fn mf(&self) -> MfR {
251        MfR::new(((self.bits >> 2) & 7) as u8)
252    }
253    #[doc = "Bits 5:7 - Modulation Depth Control"]
254    #[inline(always)]
255    pub fn mr(&self) -> MrR {
256        MrR::new(((self.bits >> 5) & 7) as u8)
257    }
258    #[doc = "Bits 8:9 - Modulation Waveform Control"]
259    #[inline(always)]
260    pub fn mc(&self) -> McR {
261        McR::new(((self.bits >> 8) & 3) as u8)
262    }
263    #[doc = "Bit 10 - Dither Enable"]
264    #[inline(always)]
265    pub fn dither(&self) -> DitherR {
266        DitherR::new(((self.bits >> 10) & 1) != 0)
267    }
268    #[doc = "Bit 11 - SS_MDIV select."]
269    #[inline(always)]
270    pub fn sel_ss_mdiv(&self) -> SelSsMdivR {
271        SelSsMdivR::new(((self.bits >> 11) & 1) != 0)
272    }
273    #[doc = "Bit 31 - SSCG Power Down"]
274    #[inline(always)]
275    pub fn ss_pd(&self) -> SsPdR {
276        SsPdR::new(((self.bits >> 31) & 1) != 0)
277    }
278}
279#[cfg(feature = "debug")]
280impl core::fmt::Debug for R {
281    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
282        f.debug_struct("SPLLSSCG1")
283            .field("ss_mdiv_msb", &self.ss_mdiv_msb())
284            .field("ss_mdiv_req", &self.ss_mdiv_req())
285            .field("mf", &self.mf())
286            .field("mr", &self.mr())
287            .field("mc", &self.mc())
288            .field("dither", &self.dither())
289            .field("sel_ss_mdiv", &self.sel_ss_mdiv())
290            .field("ss_pd", &self.ss_pd())
291            .finish()
292    }
293}
294impl W {
295    #[doc = "Bit 0 - SS_MDIV\\[32\\]"]
296    #[inline(always)]
297    pub fn ss_mdiv_msb(&mut self) -> SsMdivMsbW<'_, Spllsscg1Spec> {
298        SsMdivMsbW::new(self, 0)
299    }
300    #[doc = "Bit 1 - SS_MDIV\\[32:0\\] change request."]
301    #[inline(always)]
302    pub fn ss_mdiv_req(&mut self) -> SsMdivReqW<'_, Spllsscg1Spec> {
303        SsMdivReqW::new(self, 1)
304    }
305    #[doc = "Bits 2:4 - Modulation Frequency Control"]
306    #[inline(always)]
307    pub fn mf(&mut self) -> MfW<'_, Spllsscg1Spec> {
308        MfW::new(self, 2)
309    }
310    #[doc = "Bits 5:7 - Modulation Depth Control"]
311    #[inline(always)]
312    pub fn mr(&mut self) -> MrW<'_, Spllsscg1Spec> {
313        MrW::new(self, 5)
314    }
315    #[doc = "Bits 8:9 - Modulation Waveform Control"]
316    #[inline(always)]
317    pub fn mc(&mut self) -> McW<'_, Spllsscg1Spec> {
318        McW::new(self, 8)
319    }
320    #[doc = "Bit 10 - Dither Enable"]
321    #[inline(always)]
322    pub fn dither(&mut self) -> DitherW<'_, Spllsscg1Spec> {
323        DitherW::new(self, 10)
324    }
325    #[doc = "Bit 11 - SS_MDIV select."]
326    #[inline(always)]
327    pub fn sel_ss_mdiv(&mut self) -> SelSsMdivW<'_, Spllsscg1Spec> {
328        SelSsMdivW::new(self, 11)
329    }
330    #[doc = "Bit 31 - SSCG Power Down"]
331    #[inline(always)]
332    pub fn ss_pd(&mut self) -> SsPdW<'_, Spllsscg1Spec> {
333        SsPdW::new(self, 31)
334    }
335}
336#[doc = "SPLL Spread Spectrum Control 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
337pub struct Spllsscg1Spec;
338impl crate::RegisterSpec for Spllsscg1Spec {
339    type Ux = u32;
340}
341#[doc = "`read()` method returns [`spllsscg1::R`](R) reader structure"]
342impl crate::Readable for Spllsscg1Spec {}
343#[doc = "`write(|w| ..)` method takes [`spllsscg1::W`](W) writer structure"]
344impl crate::Writable for Spllsscg1Spec {
345    type Safety = crate::Unsafe;
346}
347#[doc = "`reset()` method sets SPLLSSCG1 to value 0x8000_0000"]
348impl crate::Resettable for Spllsscg1Spec {
349    const RESET_VALUE: u32 = 0x8000_0000;
350}
mcxa_pac/scg0/spllsscg1.rs

mcxa_pac/scg0/
spllsscg1.rs
