mcxa_pac/scg0/
sirccsr.rs

1#[doc = "Register `SIRCCSR` reader"]
2pub type R = crate::R<SirccsrSpec>;
3#[doc = "Register `SIRCCSR` writer"]
4pub type W = crate::W<SirccsrSpec>;
5#[doc = "SIRC Stop Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Sircsten {
9    #[doc = "0: SIRC is disabled in Deep Sleep mode"]
10    Disabled = 0,
11    #[doc = "1: SIRC is enabled in Deep Sleep mode"]
12    Enabled = 1,
13}
14impl From<Sircsten> for bool {
15    #[inline(always)]
16    fn from(variant: Sircsten) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `SIRCSTEN` reader - SIRC Stop Enable"]
21pub type SircstenR = crate::BitReader<Sircsten>;
22impl SircstenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Sircsten {
26        match self.bits {
27            false => Sircsten::Disabled,
28            true => Sircsten::Enabled,
29        }
30    }
31    #[doc = "SIRC is disabled in Deep Sleep mode"]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Sircsten::Disabled
35    }
36    #[doc = "SIRC is enabled in Deep Sleep mode"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Sircsten::Enabled
40    }
41}
42#[doc = "Field `SIRCSTEN` writer - SIRC Stop Enable"]
43pub type SircstenW<'a, REG> = crate::BitWriter<'a, REG, Sircsten>;
44impl<'a, REG> SircstenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "SIRC is disabled in Deep Sleep mode"]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Sircsten::Disabled)
52    }
53    #[doc = "SIRC is enabled in Deep Sleep mode"]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Sircsten::Enabled)
57    }
58}
59#[doc = "SIRC Clock to Peripherals Enable\n\nValue on reset: 1"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum SircClkPeriphEn {
63    #[doc = "0: SIRC clock to peripherals is disabled"]
64    Disabled = 0,
65    #[doc = "1: SIRC clock to peripherals is enabled"]
66    Enabled = 1,
67}
68impl From<SircClkPeriphEn> for bool {
69    #[inline(always)]
70    fn from(variant: SircClkPeriphEn) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `SIRC_CLK_PERIPH_EN` reader - SIRC Clock to Peripherals Enable"]
75pub type SircClkPeriphEnR = crate::BitReader<SircClkPeriphEn>;
76impl SircClkPeriphEnR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> SircClkPeriphEn {
80        match self.bits {
81            false => SircClkPeriphEn::Disabled,
82            true => SircClkPeriphEn::Enabled,
83        }
84    }
85    #[doc = "SIRC clock to peripherals is disabled"]
86    #[inline(always)]
87    pub fn is_disabled(&self) -> bool {
88        *self == SircClkPeriphEn::Disabled
89    }
90    #[doc = "SIRC clock to peripherals is enabled"]
91    #[inline(always)]
92    pub fn is_enabled(&self) -> bool {
93        *self == SircClkPeriphEn::Enabled
94    }
95}
96#[doc = "Field `SIRC_CLK_PERIPH_EN` writer - SIRC Clock to Peripherals Enable"]
97pub type SircClkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, SircClkPeriphEn>;
98impl<'a, REG> SircClkPeriphEnW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "SIRC clock to peripherals is disabled"]
103    #[inline(always)]
104    pub fn disabled(self) -> &'a mut crate::W<REG> {
105        self.variant(SircClkPeriphEn::Disabled)
106    }
107    #[doc = "SIRC clock to peripherals is enabled"]
108    #[inline(always)]
109    pub fn enabled(self) -> &'a mut crate::W<REG> {
110        self.variant(SircClkPeriphEn::Enabled)
111    }
112}
113#[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Sirctren {
117    #[doc = "0: Disables trimming SIRC to an external clock source"]
118    Disabled = 0,
119    #[doc = "1: Enables trimming SIRC to an external clock source"]
120    Enabled = 1,
121}
122impl From<Sirctren> for bool {
123    #[inline(always)]
124    fn from(variant: Sirctren) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `SIRCTREN` reader - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"]
129pub type SirctrenR = crate::BitReader<Sirctren>;
130impl SirctrenR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Sirctren {
134        match self.bits {
135            false => Sirctren::Disabled,
136            true => Sirctren::Enabled,
137        }
138    }
139    #[doc = "Disables trimming SIRC to an external clock source"]
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == Sirctren::Disabled
143    }
144    #[doc = "Enables trimming SIRC to an external clock source"]
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == Sirctren::Enabled
148    }
149}
150#[doc = "Field `SIRCTREN` writer - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"]
151pub type SirctrenW<'a, REG> = crate::BitWriter<'a, REG, Sirctren>;
152impl<'a, REG> SirctrenW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Disables trimming SIRC to an external clock source"]
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(Sirctren::Disabled)
160    }
161    #[doc = "Enables trimming SIRC to an external clock source"]
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(Sirctren::Enabled)
165    }
166}
167#[doc = "SIRC Trim Update\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Sirctrup {
171    #[doc = "0: Disables SIRC trimming updates"]
172    Disabled = 0,
173    #[doc = "1: Enables SIRC trimming updates"]
174    Enabled = 1,
175}
176impl From<Sirctrup> for bool {
177    #[inline(always)]
178    fn from(variant: Sirctrup) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `SIRCTRUP` reader - SIRC Trim Update"]
183pub type SirctrupR = crate::BitReader<Sirctrup>;
184impl SirctrupR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Sirctrup {
188        match self.bits {
189            false => Sirctrup::Disabled,
190            true => Sirctrup::Enabled,
191        }
192    }
193    #[doc = "Disables SIRC trimming updates"]
194    #[inline(always)]
195    pub fn is_disabled(&self) -> bool {
196        *self == Sirctrup::Disabled
197    }
198    #[doc = "Enables SIRC trimming updates"]
199    #[inline(always)]
200    pub fn is_enabled(&self) -> bool {
201        *self == Sirctrup::Enabled
202    }
203}
204#[doc = "Field `SIRCTRUP` writer - SIRC Trim Update"]
205pub type SirctrupW<'a, REG> = crate::BitWriter<'a, REG, Sirctrup>;
206impl<'a, REG> SirctrupW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Disables SIRC trimming updates"]
211    #[inline(always)]
212    pub fn disabled(self) -> &'a mut crate::W<REG> {
213        self.variant(Sirctrup::Disabled)
214    }
215    #[doc = "Enables SIRC trimming updates"]
216    #[inline(always)]
217    pub fn enabled(self) -> &'a mut crate::W<REG> {
218        self.variant(Sirctrup::Enabled)
219    }
220}
221#[doc = "SIRC TRIM LOCK\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum TrimLock {
225    #[doc = "0: SIRC auto trim not locked to target frequency range"]
226    SircNotLocked = 0,
227    #[doc = "1: SIRC auto trim locked to target frequency range"]
228    SircLocked = 1,
229}
230impl From<TrimLock> for bool {
231    #[inline(always)]
232    fn from(variant: TrimLock) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `TRIM_LOCK` reader - SIRC TRIM LOCK"]
237pub type TrimLockR = crate::BitReader<TrimLock>;
238impl TrimLockR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> TrimLock {
242        match self.bits {
243            false => TrimLock::SircNotLocked,
244            true => TrimLock::SircLocked,
245        }
246    }
247    #[doc = "SIRC auto trim not locked to target frequency range"]
248    #[inline(always)]
249    pub fn is_sirc_not_locked(&self) -> bool {
250        *self == TrimLock::SircNotLocked
251    }
252    #[doc = "SIRC auto trim locked to target frequency range"]
253    #[inline(always)]
254    pub fn is_sirc_locked(&self) -> bool {
255        *self == TrimLock::SircLocked
256    }
257}
258#[doc = "Coarse Auto Trim Bypass\n\nValue on reset: 0"]
259#[cfg_attr(feature = "defmt", derive(defmt::Format))]
260#[derive(Clone, Copy, Debug, PartialEq, Eq)]
261pub enum CoarseTrimBypass {
262    #[doc = "0: SIRC Coarse Auto Trim NOT Bypassed"]
263    NotBypassed = 0,
264    #[doc = "1: SIRC Coarse Auto Trim Bypassed"]
265    Bypassed = 1,
266}
267impl From<CoarseTrimBypass> for bool {
268    #[inline(always)]
269    fn from(variant: CoarseTrimBypass) -> Self {
270        variant as u8 != 0
271    }
272}
273#[doc = "Field `COARSE_TRIM_BYPASS` reader - Coarse Auto Trim Bypass"]
274pub type CoarseTrimBypassR = crate::BitReader<CoarseTrimBypass>;
275impl CoarseTrimBypassR {
276    #[doc = "Get enumerated values variant"]
277    #[inline(always)]
278    pub const fn variant(&self) -> CoarseTrimBypass {
279        match self.bits {
280            false => CoarseTrimBypass::NotBypassed,
281            true => CoarseTrimBypass::Bypassed,
282        }
283    }
284    #[doc = "SIRC Coarse Auto Trim NOT Bypassed"]
285    #[inline(always)]
286    pub fn is_not_bypassed(&self) -> bool {
287        *self == CoarseTrimBypass::NotBypassed
288    }
289    #[doc = "SIRC Coarse Auto Trim Bypassed"]
290    #[inline(always)]
291    pub fn is_bypassed(&self) -> bool {
292        *self == CoarseTrimBypass::Bypassed
293    }
294}
295#[doc = "Field `COARSE_TRIM_BYPASS` writer - Coarse Auto Trim Bypass"]
296pub type CoarseTrimBypassW<'a, REG> = crate::BitWriter<'a, REG, CoarseTrimBypass>;
297impl<'a, REG> CoarseTrimBypassW<'a, REG>
298where
299    REG: crate::Writable + crate::RegisterSpec,
300{
301    #[doc = "SIRC Coarse Auto Trim NOT Bypassed"]
302    #[inline(always)]
303    pub fn not_bypassed(self) -> &'a mut crate::W<REG> {
304        self.variant(CoarseTrimBypass::NotBypassed)
305    }
306    #[doc = "SIRC Coarse Auto Trim Bypassed"]
307    #[inline(always)]
308    pub fn bypassed(self) -> &'a mut crate::W<REG> {
309        self.variant(CoarseTrimBypass::Bypassed)
310    }
311}
312#[doc = "Lock Register\n\nValue on reset: 0"]
313#[cfg_attr(feature = "defmt", derive(defmt::Format))]
314#[derive(Clone, Copy, Debug, PartialEq, Eq)]
315pub enum Lk {
316    #[doc = "0: Control Status Register can be written"]
317    WriteEnabled = 0,
318    #[doc = "1: Control Status Register cannot be written"]
319    WriteDisabled = 1,
320}
321impl From<Lk> for bool {
322    #[inline(always)]
323    fn from(variant: Lk) -> Self {
324        variant as u8 != 0
325    }
326}
327#[doc = "Field `LK` reader - Lock Register"]
328pub type LkR = crate::BitReader<Lk>;
329impl LkR {
330    #[doc = "Get enumerated values variant"]
331    #[inline(always)]
332    pub const fn variant(&self) -> Lk {
333        match self.bits {
334            false => Lk::WriteEnabled,
335            true => Lk::WriteDisabled,
336        }
337    }
338    #[doc = "Control Status Register can be written"]
339    #[inline(always)]
340    pub fn is_write_enabled(&self) -> bool {
341        *self == Lk::WriteEnabled
342    }
343    #[doc = "Control Status Register cannot be written"]
344    #[inline(always)]
345    pub fn is_write_disabled(&self) -> bool {
346        *self == Lk::WriteDisabled
347    }
348}
349#[doc = "Field `LK` writer - Lock Register"]
350pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>;
351impl<'a, REG> LkW<'a, REG>
352where
353    REG: crate::Writable + crate::RegisterSpec,
354{
355    #[doc = "Control Status Register can be written"]
356    #[inline(always)]
357    pub fn write_enabled(self) -> &'a mut crate::W<REG> {
358        self.variant(Lk::WriteEnabled)
359    }
360    #[doc = "Control Status Register cannot be written"]
361    #[inline(always)]
362    pub fn write_disabled(self) -> &'a mut crate::W<REG> {
363        self.variant(Lk::WriteDisabled)
364    }
365}
366#[doc = "SIRC Valid\n\nValue on reset: 1"]
367#[cfg_attr(feature = "defmt", derive(defmt::Format))]
368#[derive(Clone, Copy, Debug, PartialEq, Eq)]
369pub enum Sircvld {
370    #[doc = "0: SIRC is not enabled or clock is not valid"]
371    DisabledOrNotValid = 0,
372    #[doc = "1: SIRC is enabled and output clock is valid"]
373    EnabledAndValid = 1,
374}
375impl From<Sircvld> for bool {
376    #[inline(always)]
377    fn from(variant: Sircvld) -> Self {
378        variant as u8 != 0
379    }
380}
381#[doc = "Field `SIRCVLD` reader - SIRC Valid"]
382pub type SircvldR = crate::BitReader<Sircvld>;
383impl SircvldR {
384    #[doc = "Get enumerated values variant"]
385    #[inline(always)]
386    pub const fn variant(&self) -> Sircvld {
387        match self.bits {
388            false => Sircvld::DisabledOrNotValid,
389            true => Sircvld::EnabledAndValid,
390        }
391    }
392    #[doc = "SIRC is not enabled or clock is not valid"]
393    #[inline(always)]
394    pub fn is_disabled_or_not_valid(&self) -> bool {
395        *self == Sircvld::DisabledOrNotValid
396    }
397    #[doc = "SIRC is enabled and output clock is valid"]
398    #[inline(always)]
399    pub fn is_enabled_and_valid(&self) -> bool {
400        *self == Sircvld::EnabledAndValid
401    }
402}
403#[doc = "SIRC Selected\n\nValue on reset: 0"]
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum Sircsel {
407    #[doc = "0: SIRC is not the system clock source"]
408    NotSirc = 0,
409    #[doc = "1: SIRC is the system clock source"]
410    Sirc = 1,
411}
412impl From<Sircsel> for bool {
413    #[inline(always)]
414    fn from(variant: Sircsel) -> Self {
415        variant as u8 != 0
416    }
417}
418#[doc = "Field `SIRCSEL` reader - SIRC Selected"]
419pub type SircselR = crate::BitReader<Sircsel>;
420impl SircselR {
421    #[doc = "Get enumerated values variant"]
422    #[inline(always)]
423    pub const fn variant(&self) -> Sircsel {
424        match self.bits {
425            false => Sircsel::NotSirc,
426            true => Sircsel::Sirc,
427        }
428    }
429    #[doc = "SIRC is not the system clock source"]
430    #[inline(always)]
431    pub fn is_not_sirc(&self) -> bool {
432        *self == Sircsel::NotSirc
433    }
434    #[doc = "SIRC is the system clock source"]
435    #[inline(always)]
436    pub fn is_sirc(&self) -> bool {
437        *self == Sircsel::Sirc
438    }
439}
440#[doc = "SIRC Clock Error\n\nValue on reset: 0"]
441#[cfg_attr(feature = "defmt", derive(defmt::Format))]
442#[derive(Clone, Copy, Debug, PartialEq, Eq)]
443pub enum Sircerr {
444    #[doc = "0: Error not detected with the SIRC trimming"]
445    ErrorNotDetected = 0,
446    #[doc = "1: Error detected with the SIRC trimming"]
447    ErrorDetected = 1,
448}
449impl From<Sircerr> for bool {
450    #[inline(always)]
451    fn from(variant: Sircerr) -> Self {
452        variant as u8 != 0
453    }
454}
455#[doc = "Field `SIRCERR` reader - SIRC Clock Error"]
456pub type SircerrR = crate::BitReader<Sircerr>;
457impl SircerrR {
458    #[doc = "Get enumerated values variant"]
459    #[inline(always)]
460    pub const fn variant(&self) -> Sircerr {
461        match self.bits {
462            false => Sircerr::ErrorNotDetected,
463            true => Sircerr::ErrorDetected,
464        }
465    }
466    #[doc = "Error not detected with the SIRC trimming"]
467    #[inline(always)]
468    pub fn is_error_not_detected(&self) -> bool {
469        *self == Sircerr::ErrorNotDetected
470    }
471    #[doc = "Error detected with the SIRC trimming"]
472    #[inline(always)]
473    pub fn is_error_detected(&self) -> bool {
474        *self == Sircerr::ErrorDetected
475    }
476}
477#[doc = "Field `SIRCERR` writer - SIRC Clock Error"]
478pub type SircerrW<'a, REG> = crate::BitWriter1C<'a, REG, Sircerr>;
479impl<'a, REG> SircerrW<'a, REG>
480where
481    REG: crate::Writable + crate::RegisterSpec,
482{
483    #[doc = "Error not detected with the SIRC trimming"]
484    #[inline(always)]
485    pub fn error_not_detected(self) -> &'a mut crate::W<REG> {
486        self.variant(Sircerr::ErrorNotDetected)
487    }
488    #[doc = "Error detected with the SIRC trimming"]
489    #[inline(always)]
490    pub fn error_detected(self) -> &'a mut crate::W<REG> {
491        self.variant(Sircerr::ErrorDetected)
492    }
493}
494#[doc = "SIRC Clock Error Interrupt Enable\n\nValue on reset: 0"]
495#[cfg_attr(feature = "defmt", derive(defmt::Format))]
496#[derive(Clone, Copy, Debug, PartialEq, Eq)]
497pub enum SircerrIe {
498    #[doc = "0: SIRCERR interrupt is not enabled"]
499    ErrorNotDetected = 0,
500    #[doc = "1: SIRCERR interrupt is enabled"]
501    ErrorDetected = 1,
502}
503impl From<SircerrIe> for bool {
504    #[inline(always)]
505    fn from(variant: SircerrIe) -> Self {
506        variant as u8 != 0
507    }
508}
509#[doc = "Field `SIRCERR_IE` reader - SIRC Clock Error Interrupt Enable"]
510pub type SircerrIeR = crate::BitReader<SircerrIe>;
511impl SircerrIeR {
512    #[doc = "Get enumerated values variant"]
513    #[inline(always)]
514    pub const fn variant(&self) -> SircerrIe {
515        match self.bits {
516            false => SircerrIe::ErrorNotDetected,
517            true => SircerrIe::ErrorDetected,
518        }
519    }
520    #[doc = "SIRCERR interrupt is not enabled"]
521    #[inline(always)]
522    pub fn is_error_not_detected(&self) -> bool {
523        *self == SircerrIe::ErrorNotDetected
524    }
525    #[doc = "SIRCERR interrupt is enabled"]
526    #[inline(always)]
527    pub fn is_error_detected(&self) -> bool {
528        *self == SircerrIe::ErrorDetected
529    }
530}
531#[doc = "Field `SIRCERR_IE` writer - SIRC Clock Error Interrupt Enable"]
532pub type SircerrIeW<'a, REG> = crate::BitWriter<'a, REG, SircerrIe>;
533impl<'a, REG> SircerrIeW<'a, REG>
534where
535    REG: crate::Writable + crate::RegisterSpec,
536{
537    #[doc = "SIRCERR interrupt is not enabled"]
538    #[inline(always)]
539    pub fn error_not_detected(self) -> &'a mut crate::W<REG> {
540        self.variant(SircerrIe::ErrorNotDetected)
541    }
542    #[doc = "SIRCERR interrupt is enabled"]
543    #[inline(always)]
544    pub fn error_detected(self) -> &'a mut crate::W<REG> {
545        self.variant(SircerrIe::ErrorDetected)
546    }
547}
548impl R {
549    #[doc = "Bit 1 - SIRC Stop Enable"]
550    #[inline(always)]
551    pub fn sircsten(&self) -> SircstenR {
552        SircstenR::new(((self.bits >> 1) & 1) != 0)
553    }
554    #[doc = "Bit 5 - SIRC Clock to Peripherals Enable"]
555    #[inline(always)]
556    pub fn sirc_clk_periph_en(&self) -> SircClkPeriphEnR {
557        SircClkPeriphEnR::new(((self.bits >> 5) & 1) != 0)
558    }
559    #[doc = "Bit 8 - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"]
560    #[inline(always)]
561    pub fn sirctren(&self) -> SirctrenR {
562        SirctrenR::new(((self.bits >> 8) & 1) != 0)
563    }
564    #[doc = "Bit 9 - SIRC Trim Update"]
565    #[inline(always)]
566    pub fn sirctrup(&self) -> SirctrupR {
567        SirctrupR::new(((self.bits >> 9) & 1) != 0)
568    }
569    #[doc = "Bit 10 - SIRC TRIM LOCK"]
570    #[inline(always)]
571    pub fn trim_lock(&self) -> TrimLockR {
572        TrimLockR::new(((self.bits >> 10) & 1) != 0)
573    }
574    #[doc = "Bit 11 - Coarse Auto Trim Bypass"]
575    #[inline(always)]
576    pub fn coarse_trim_bypass(&self) -> CoarseTrimBypassR {
577        CoarseTrimBypassR::new(((self.bits >> 11) & 1) != 0)
578    }
579    #[doc = "Bit 23 - Lock Register"]
580    #[inline(always)]
581    pub fn lk(&self) -> LkR {
582        LkR::new(((self.bits >> 23) & 1) != 0)
583    }
584    #[doc = "Bit 24 - SIRC Valid"]
585    #[inline(always)]
586    pub fn sircvld(&self) -> SircvldR {
587        SircvldR::new(((self.bits >> 24) & 1) != 0)
588    }
589    #[doc = "Bit 25 - SIRC Selected"]
590    #[inline(always)]
591    pub fn sircsel(&self) -> SircselR {
592        SircselR::new(((self.bits >> 25) & 1) != 0)
593    }
594    #[doc = "Bit 26 - SIRC Clock Error"]
595    #[inline(always)]
596    pub fn sircerr(&self) -> SircerrR {
597        SircerrR::new(((self.bits >> 26) & 1) != 0)
598    }
599    #[doc = "Bit 27 - SIRC Clock Error Interrupt Enable"]
600    #[inline(always)]
601    pub fn sircerr_ie(&self) -> SircerrIeR {
602        SircerrIeR::new(((self.bits >> 27) & 1) != 0)
603    }
604}
605#[cfg(feature = "debug")]
606impl core::fmt::Debug for R {
607    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
608        f.debug_struct("SIRCCSR")
609            .field("sircsten", &self.sircsten())
610            .field("sirc_clk_periph_en", &self.sirc_clk_periph_en())
611            .field("sirctren", &self.sirctren())
612            .field("sirctrup", &self.sirctrup())
613            .field("trim_lock", &self.trim_lock())
614            .field("coarse_trim_bypass", &self.coarse_trim_bypass())
615            .field("lk", &self.lk())
616            .field("sircvld", &self.sircvld())
617            .field("sircsel", &self.sircsel())
618            .field("sircerr", &self.sircerr())
619            .field("sircerr_ie", &self.sircerr_ie())
620            .finish()
621    }
622}
623impl W {
624    #[doc = "Bit 1 - SIRC Stop Enable"]
625    #[inline(always)]
626    pub fn sircsten(&mut self) -> SircstenW<'_, SirccsrSpec> {
627        SircstenW::new(self, 1)
628    }
629    #[doc = "Bit 5 - SIRC Clock to Peripherals Enable"]
630    #[inline(always)]
631    pub fn sirc_clk_periph_en(&mut self) -> SircClkPeriphEnW<'_, SirccsrSpec> {
632        SircClkPeriphEnW::new(self, 5)
633    }
634    #[doc = "Bit 8 - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"]
635    #[inline(always)]
636    pub fn sirctren(&mut self) -> SirctrenW<'_, SirccsrSpec> {
637        SirctrenW::new(self, 8)
638    }
639    #[doc = "Bit 9 - SIRC Trim Update"]
640    #[inline(always)]
641    pub fn sirctrup(&mut self) -> SirctrupW<'_, SirccsrSpec> {
642        SirctrupW::new(self, 9)
643    }
644    #[doc = "Bit 11 - Coarse Auto Trim Bypass"]
645    #[inline(always)]
646    pub fn coarse_trim_bypass(&mut self) -> CoarseTrimBypassW<'_, SirccsrSpec> {
647        CoarseTrimBypassW::new(self, 11)
648    }
649    #[doc = "Bit 23 - Lock Register"]
650    #[inline(always)]
651    pub fn lk(&mut self) -> LkW<'_, SirccsrSpec> {
652        LkW::new(self, 23)
653    }
654    #[doc = "Bit 26 - SIRC Clock Error"]
655    #[inline(always)]
656    pub fn sircerr(&mut self) -> SircerrW<'_, SirccsrSpec> {
657        SircerrW::new(self, 26)
658    }
659    #[doc = "Bit 27 - SIRC Clock Error Interrupt Enable"]
660    #[inline(always)]
661    pub fn sircerr_ie(&mut self) -> SircerrIeW<'_, SirccsrSpec> {
662        SircerrIeW::new(self, 27)
663    }
664}
665#[doc = "SIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
666pub struct SirccsrSpec;
667impl crate::RegisterSpec for SirccsrSpec {
668    type Ux = u32;
669}
670#[doc = "`read()` method returns [`sirccsr::R`](R) reader structure"]
671impl crate::Readable for SirccsrSpec {}
672#[doc = "`write(|w| ..)` method takes [`sirccsr::W`](W) writer structure"]
673impl crate::Writable for SirccsrSpec {
674    type Safety = crate::Unsafe;
675    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000;
676}
677#[doc = "`reset()` method sets SIRCCSR to value 0x0100_0020"]
678impl crate::Resettable for SirccsrSpec {
679    const RESET_VALUE: u32 = 0x0100_0020;
680}
mcxa_pac/scg0/sirccsr.rs

mcxa_pac/scg0/
sirccsr.rs
