mcxa_pac/scg0/
firccfg.rs

1#[doc = "Register `FIRCCFG` reader"]
2pub type R = crate::R<FirccfgSpec>;
3#[doc = "Register `FIRCCFG` writer"]
4pub type W = crate::W<FirccfgSpec>;
5#[doc = "Frequency select\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum FreqSel {
10    #[doc = "1: 45 MHz FIRC clock selected, divided from 180 MHz"]
11    Firc48mhz192s = 1,
12    #[doc = "3: 60 MHz FIRC clock selected"]
13    Firc64mhz = 3,
14    #[doc = "5: 90 MHz FIRC clock selected"]
15    Firc96mhz = 5,
16    #[doc = "7: 180 MHz FIRC clock selected"]
17    Firc192mhz = 7,
18}
19impl From<FreqSel> for u8 {
20    #[inline(always)]
21    fn from(variant: FreqSel) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for FreqSel {
26    type Ux = u8;
27}
28impl crate::IsEnum for FreqSel {}
29#[doc = "Field `FREQ_SEL` reader - Frequency select"]
30pub type FreqSelR = crate::FieldReader<FreqSel>;
31impl FreqSelR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<FreqSel> {
35        match self.bits {
36            1 => Some(FreqSel::Firc48mhz192s),
37            3 => Some(FreqSel::Firc64mhz),
38            5 => Some(FreqSel::Firc96mhz),
39            7 => Some(FreqSel::Firc192mhz),
40            _ => None,
41        }
42    }
43    #[doc = "45 MHz FIRC clock selected, divided from 180 MHz"]
44    #[inline(always)]
45    pub fn is_firc_48mhz_192s(&self) -> bool {
46        *self == FreqSel::Firc48mhz192s
47    }
48    #[doc = "60 MHz FIRC clock selected"]
49    #[inline(always)]
50    pub fn is_firc_64mhz(&self) -> bool {
51        *self == FreqSel::Firc64mhz
52    }
53    #[doc = "90 MHz FIRC clock selected"]
54    #[inline(always)]
55    pub fn is_firc_96mhz(&self) -> bool {
56        *self == FreqSel::Firc96mhz
57    }
58    #[doc = "180 MHz FIRC clock selected"]
59    #[inline(always)]
60    pub fn is_firc_192mhz(&self) -> bool {
61        *self == FreqSel::Firc192mhz
62    }
63}
64#[doc = "Field `FREQ_SEL` writer - Frequency select"]
65pub type FreqSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, FreqSel>;
66impl<'a, REG> FreqSelW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "45 MHz FIRC clock selected, divided from 180 MHz"]
72    #[inline(always)]
73    pub fn firc_48mhz_192s(self) -> &'a mut crate::W<REG> {
74        self.variant(FreqSel::Firc48mhz192s)
75    }
76    #[doc = "60 MHz FIRC clock selected"]
77    #[inline(always)]
78    pub fn firc_64mhz(self) -> &'a mut crate::W<REG> {
79        self.variant(FreqSel::Firc64mhz)
80    }
81    #[doc = "90 MHz FIRC clock selected"]
82    #[inline(always)]
83    pub fn firc_96mhz(self) -> &'a mut crate::W<REG> {
84        self.variant(FreqSel::Firc96mhz)
85    }
86    #[doc = "180 MHz FIRC clock selected"]
87    #[inline(always)]
88    pub fn firc_192mhz(self) -> &'a mut crate::W<REG> {
89        self.variant(FreqSel::Firc192mhz)
90    }
91}
92impl R {
93    #[doc = "Bits 1:3 - Frequency select"]
94    #[inline(always)]
95    pub fn freq_sel(&self) -> FreqSelR {
96        FreqSelR::new(((self.bits >> 1) & 7) as u8)
97    }
98}
99#[cfg(feature = "debug")]
100impl core::fmt::Debug for R {
101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102        f.debug_struct("FIRCCFG").field("freq_sel", &self.freq_sel()).finish()
103    }
104}
105impl W {
106    #[doc = "Bits 1:3 - Frequency select"]
107    #[inline(always)]
108    pub fn freq_sel(&mut self) -> FreqSelW<'_, FirccfgSpec> {
109        FreqSelW::new(self, 1)
110    }
111}
112#[doc = "FIRC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
113pub struct FirccfgSpec;
114impl crate::RegisterSpec for FirccfgSpec {
115    type Ux = u32;
116}
117#[doc = "`read()` method returns [`firccfg::R`](R) reader structure"]
118impl crate::Readable for FirccfgSpec {}
119#[doc = "`write(|w| ..)` method takes [`firccfg::W`](W) writer structure"]
120impl crate::Writable for FirccfgSpec {
121    type Safety = crate::Unsafe;
122}
123#[doc = "`reset()` method sets FIRCCFG to value 0x03"]
124impl crate::Resettable for FirccfgSpec {
125    const RESET_VALUE: u32 = 0x03;
126}
mcxa_pac/scg0/firccfg.rs

mcxa_pac/scg0/
firccfg.rs
