mcxa_pac/rtc0/
lr.rs

1#[doc = "Register `LR` reader"]
2pub type R = crate::R<LrSpec>;
3#[doc = "Register `LR` writer"]
4pub type W = crate::W<LrSpec>;
5#[doc = "Time Compensation Lock\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Tcl {
9    #[doc = "0: Time Compensation Register is locked and writes are ignored."]
10    Tcl0 = 0,
11    #[doc = "1: Time Compensation Register is not locked and writes complete as normal."]
12    Tcl1 = 1,
13}
14impl From<Tcl> for bool {
15    #[inline(always)]
16    fn from(variant: Tcl) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `TCL` reader - Time Compensation Lock"]
21pub type TclR = crate::BitReader<Tcl>;
22impl TclR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Tcl {
26        match self.bits {
27            false => Tcl::Tcl0,
28            true => Tcl::Tcl1,
29        }
30    }
31    #[doc = "Time Compensation Register is locked and writes are ignored."]
32    #[inline(always)]
33    pub fn is_tcl_0(&self) -> bool {
34        *self == Tcl::Tcl0
35    }
36    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
37    #[inline(always)]
38    pub fn is_tcl_1(&self) -> bool {
39        *self == Tcl::Tcl1
40    }
41}
42#[doc = "Field `TCL` writer - Time Compensation Lock"]
43pub type TclW<'a, REG> = crate::BitWriter<'a, REG, Tcl>;
44impl<'a, REG> TclW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Time Compensation Register is locked and writes are ignored."]
49    #[inline(always)]
50    pub fn tcl_0(self) -> &'a mut crate::W<REG> {
51        self.variant(Tcl::Tcl0)
52    }
53    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
54    #[inline(always)]
55    pub fn tcl_1(self) -> &'a mut crate::W<REG> {
56        self.variant(Tcl::Tcl1)
57    }
58}
59#[doc = "Control Register Lock\n\nValue on reset: 1"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Crl {
63    #[doc = "0: Control Register is locked and writes are ignored."]
64    Crl0 = 0,
65    #[doc = "1: Control Register is not locked and writes complete as normal."]
66    Crl1 = 1,
67}
68impl From<Crl> for bool {
69    #[inline(always)]
70    fn from(variant: Crl) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `CRL` reader - Control Register Lock"]
75pub type CrlR = crate::BitReader<Crl>;
76impl CrlR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Crl {
80        match self.bits {
81            false => Crl::Crl0,
82            true => Crl::Crl1,
83        }
84    }
85    #[doc = "Control Register is locked and writes are ignored."]
86    #[inline(always)]
87    pub fn is_crl_0(&self) -> bool {
88        *self == Crl::Crl0
89    }
90    #[doc = "Control Register is not locked and writes complete as normal."]
91    #[inline(always)]
92    pub fn is_crl_1(&self) -> bool {
93        *self == Crl::Crl1
94    }
95}
96#[doc = "Field `CRL` writer - Control Register Lock"]
97pub type CrlW<'a, REG> = crate::BitWriter<'a, REG, Crl>;
98impl<'a, REG> CrlW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Control Register is locked and writes are ignored."]
103    #[inline(always)]
104    pub fn crl_0(self) -> &'a mut crate::W<REG> {
105        self.variant(Crl::Crl0)
106    }
107    #[doc = "Control Register is not locked and writes complete as normal."]
108    #[inline(always)]
109    pub fn crl_1(self) -> &'a mut crate::W<REG> {
110        self.variant(Crl::Crl1)
111    }
112}
113#[doc = "Status Register Lock\n\nValue on reset: 1"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Srl {
117    #[doc = "0: Status Register is locked and writes are ignored."]
118    Srl0 = 0,
119    #[doc = "1: Status Register is not locked and writes complete as normal."]
120    Srl1 = 1,
121}
122impl From<Srl> for bool {
123    #[inline(always)]
124    fn from(variant: Srl) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `SRL` reader - Status Register Lock"]
129pub type SrlR = crate::BitReader<Srl>;
130impl SrlR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Srl {
134        match self.bits {
135            false => Srl::Srl0,
136            true => Srl::Srl1,
137        }
138    }
139    #[doc = "Status Register is locked and writes are ignored."]
140    #[inline(always)]
141    pub fn is_srl_0(&self) -> bool {
142        *self == Srl::Srl0
143    }
144    #[doc = "Status Register is not locked and writes complete as normal."]
145    #[inline(always)]
146    pub fn is_srl_1(&self) -> bool {
147        *self == Srl::Srl1
148    }
149}
150#[doc = "Field `SRL` writer - Status Register Lock"]
151pub type SrlW<'a, REG> = crate::BitWriter<'a, REG, Srl>;
152impl<'a, REG> SrlW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Status Register is locked and writes are ignored."]
157    #[inline(always)]
158    pub fn srl_0(self) -> &'a mut crate::W<REG> {
159        self.variant(Srl::Srl0)
160    }
161    #[doc = "Status Register is not locked and writes complete as normal."]
162    #[inline(always)]
163    pub fn srl_1(self) -> &'a mut crate::W<REG> {
164        self.variant(Srl::Srl1)
165    }
166}
167#[doc = "Lock Register Lock\n\nValue on reset: 1"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Lrl {
171    #[doc = "0: Lock Register is locked and writes are ignored."]
172    Lrl0 = 0,
173    #[doc = "1: Lock Register is not locked and writes complete as normal."]
174    Lrl1 = 1,
175}
176impl From<Lrl> for bool {
177    #[inline(always)]
178    fn from(variant: Lrl) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `LRL` reader - Lock Register Lock"]
183pub type LrlR = crate::BitReader<Lrl>;
184impl LrlR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Lrl {
188        match self.bits {
189            false => Lrl::Lrl0,
190            true => Lrl::Lrl1,
191        }
192    }
193    #[doc = "Lock Register is locked and writes are ignored."]
194    #[inline(always)]
195    pub fn is_lrl_0(&self) -> bool {
196        *self == Lrl::Lrl0
197    }
198    #[doc = "Lock Register is not locked and writes complete as normal."]
199    #[inline(always)]
200    pub fn is_lrl_1(&self) -> bool {
201        *self == Lrl::Lrl1
202    }
203}
204#[doc = "Field `LRL` writer - Lock Register Lock"]
205pub type LrlW<'a, REG> = crate::BitWriter<'a, REG, Lrl>;
206impl<'a, REG> LrlW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Lock Register is locked and writes are ignored."]
211    #[inline(always)]
212    pub fn lrl_0(self) -> &'a mut crate::W<REG> {
213        self.variant(Lrl::Lrl0)
214    }
215    #[doc = "Lock Register is not locked and writes complete as normal."]
216    #[inline(always)]
217    pub fn lrl_1(self) -> &'a mut crate::W<REG> {
218        self.variant(Lrl::Lrl1)
219    }
220}
221impl R {
222    #[doc = "Bit 3 - Time Compensation Lock"]
223    #[inline(always)]
224    pub fn tcl(&self) -> TclR {
225        TclR::new(((self.bits >> 3) & 1) != 0)
226    }
227    #[doc = "Bit 4 - Control Register Lock"]
228    #[inline(always)]
229    pub fn crl(&self) -> CrlR {
230        CrlR::new(((self.bits >> 4) & 1) != 0)
231    }
232    #[doc = "Bit 5 - Status Register Lock"]
233    #[inline(always)]
234    pub fn srl(&self) -> SrlR {
235        SrlR::new(((self.bits >> 5) & 1) != 0)
236    }
237    #[doc = "Bit 6 - Lock Register Lock"]
238    #[inline(always)]
239    pub fn lrl(&self) -> LrlR {
240        LrlR::new(((self.bits >> 6) & 1) != 0)
241    }
242}
243#[cfg(feature = "debug")]
244impl core::fmt::Debug for R {
245    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
246        f.debug_struct("LR")
247            .field("tcl", &self.tcl())
248            .field("crl", &self.crl())
249            .field("srl", &self.srl())
250            .field("lrl", &self.lrl())
251            .finish()
252    }
253}
254impl W {
255    #[doc = "Bit 3 - Time Compensation Lock"]
256    #[inline(always)]
257    pub fn tcl(&mut self) -> TclW<'_, LrSpec> {
258        TclW::new(self, 3)
259    }
260    #[doc = "Bit 4 - Control Register Lock"]
261    #[inline(always)]
262    pub fn crl(&mut self) -> CrlW<'_, LrSpec> {
263        CrlW::new(self, 4)
264    }
265    #[doc = "Bit 5 - Status Register Lock"]
266    #[inline(always)]
267    pub fn srl(&mut self) -> SrlW<'_, LrSpec> {
268        SrlW::new(self, 5)
269    }
270    #[doc = "Bit 6 - Lock Register Lock"]
271    #[inline(always)]
272    pub fn lrl(&mut self) -> LrlW<'_, LrSpec> {
273        LrlW::new(self, 6)
274    }
275}
276#[doc = "RTC Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct LrSpec;
278impl crate::RegisterSpec for LrSpec {
279    type Ux = u32;
280}
281#[doc = "`read()` method returns [`lr::R`](R) reader structure"]
282impl crate::Readable for LrSpec {}
283#[doc = "`write(|w| ..)` method takes [`lr::W`](W) writer structure"]
284impl crate::Writable for LrSpec {
285    type Safety = crate::Unsafe;
286}
287#[doc = "`reset()` method sets LR to value 0xff"]
288impl crate::Resettable for LrSpec {
289    const RESET_VALUE: u32 = 0xff;
290}
mcxa_pac/rtc0/lr.rs

mcxa_pac/rtc0/
lr.rs
