mcxa_pac/rtc0/
cr.rs

1#[doc = "Register `CR` reader"]
2pub type R = crate::R<CrSpec>;
3#[doc = "Register `CR` writer"]
4pub type W = crate::W<CrSpec>;
5#[doc = "Software Reset\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Swr {
9    #[doc = "0: No effect."]
10    Swr0 = 0,
11    #[doc = "1: Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."]
12    Swr1 = 1,
13}
14impl From<Swr> for bool {
15    #[inline(always)]
16    fn from(variant: Swr) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `SWR` reader - Software Reset"]
21pub type SwrR = crate::BitReader<Swr>;
22impl SwrR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Swr {
26        match self.bits {
27            false => Swr::Swr0,
28            true => Swr::Swr1,
29        }
30    }
31    #[doc = "No effect."]
32    #[inline(always)]
33    pub fn is_swr_0(&self) -> bool {
34        *self == Swr::Swr0
35    }
36    #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."]
37    #[inline(always)]
38    pub fn is_swr_1(&self) -> bool {
39        *self == Swr::Swr1
40    }
41}
42#[doc = "Field `SWR` writer - Software Reset"]
43pub type SwrW<'a, REG> = crate::BitWriter<'a, REG, Swr>;
44impl<'a, REG> SwrW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "No effect."]
49    #[inline(always)]
50    pub fn swr_0(self) -> &'a mut crate::W<REG> {
51        self.variant(Swr::Swr0)
52    }
53    #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."]
54    #[inline(always)]
55    pub fn swr_1(self) -> &'a mut crate::W<REG> {
56        self.variant(Swr::Swr1)
57    }
58}
59#[doc = "Update Mode\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Um {
63    #[doc = "0: Registers cannot be written when locked."]
64    Um0 = 0,
65    #[doc = "1: Registers can be written when locked under limited conditions."]
66    Um1 = 1,
67}
68impl From<Um> for bool {
69    #[inline(always)]
70    fn from(variant: Um) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `UM` reader - Update Mode"]
75pub type UmR = crate::BitReader<Um>;
76impl UmR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Um {
80        match self.bits {
81            false => Um::Um0,
82            true => Um::Um1,
83        }
84    }
85    #[doc = "Registers cannot be written when locked."]
86    #[inline(always)]
87    pub fn is_um_0(&self) -> bool {
88        *self == Um::Um0
89    }
90    #[doc = "Registers can be written when locked under limited conditions."]
91    #[inline(always)]
92    pub fn is_um_1(&self) -> bool {
93        *self == Um::Um1
94    }
95}
96#[doc = "Field `UM` writer - Update Mode"]
97pub type UmW<'a, REG> = crate::BitWriter<'a, REG, Um>;
98impl<'a, REG> UmW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Registers cannot be written when locked."]
103    #[inline(always)]
104    pub fn um_0(self) -> &'a mut crate::W<REG> {
105        self.variant(Um::Um0)
106    }
107    #[doc = "Registers can be written when locked under limited conditions."]
108    #[inline(always)]
109    pub fn um_1(self) -> &'a mut crate::W<REG> {
110        self.variant(Um::Um1)
111    }
112}
113#[doc = "LPO Select\n\nValue on reset: 1"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Lpos {
117    #[doc = "0: RTC prescaler increments using 32.768 kHz clock."]
118    Lpos0 = 0,
119    #[doc = "1: RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."]
120    Lpos1 = 1,
121}
122impl From<Lpos> for bool {
123    #[inline(always)]
124    fn from(variant: Lpos) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `LPOS` reader - LPO Select"]
129pub type LposR = crate::BitReader<Lpos>;
130impl LposR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Lpos {
134        match self.bits {
135            false => Lpos::Lpos0,
136            true => Lpos::Lpos1,
137        }
138    }
139    #[doc = "RTC prescaler increments using 32.768 kHz clock."]
140    #[inline(always)]
141    pub fn is_lpos_0(&self) -> bool {
142        *self == Lpos::Lpos0
143    }
144    #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."]
145    #[inline(always)]
146    pub fn is_lpos_1(&self) -> bool {
147        *self == Lpos::Lpos1
148    }
149}
150#[doc = "Field `LPOS` writer - LPO Select"]
151pub type LposW<'a, REG> = crate::BitWriter<'a, REG, Lpos>;
152impl<'a, REG> LposW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "RTC prescaler increments using 32.768 kHz clock."]
157    #[inline(always)]
158    pub fn lpos_0(self) -> &'a mut crate::W<REG> {
159        self.variant(Lpos::Lpos0)
160    }
161    #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."]
162    #[inline(always)]
163    pub fn lpos_1(self) -> &'a mut crate::W<REG> {
164        self.variant(Lpos::Lpos1)
165    }
166}
167impl R {
168    #[doc = "Bit 0 - Software Reset"]
169    #[inline(always)]
170    pub fn swr(&self) -> SwrR {
171        SwrR::new((self.bits & 1) != 0)
172    }
173    #[doc = "Bit 3 - Update Mode"]
174    #[inline(always)]
175    pub fn um(&self) -> UmR {
176        UmR::new(((self.bits >> 3) & 1) != 0)
177    }
178    #[doc = "Bit 7 - LPO Select"]
179    #[inline(always)]
180    pub fn lpos(&self) -> LposR {
181        LposR::new(((self.bits >> 7) & 1) != 0)
182    }
183}
184#[cfg(feature = "debug")]
185impl core::fmt::Debug for R {
186    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
187        f.debug_struct("CR")
188            .field("swr", &self.swr())
189            .field("um", &self.um())
190            .field("lpos", &self.lpos())
191            .finish()
192    }
193}
194impl W {
195    #[doc = "Bit 0 - Software Reset"]
196    #[inline(always)]
197    pub fn swr(&mut self) -> SwrW<'_, CrSpec> {
198        SwrW::new(self, 0)
199    }
200    #[doc = "Bit 3 - Update Mode"]
201    #[inline(always)]
202    pub fn um(&mut self) -> UmW<'_, CrSpec> {
203        UmW::new(self, 3)
204    }
205    #[doc = "Bit 7 - LPO Select"]
206    #[inline(always)]
207    pub fn lpos(&mut self) -> LposW<'_, CrSpec> {
208        LposW::new(self, 7)
209    }
210}
211#[doc = "RTC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct CrSpec;
213impl crate::RegisterSpec for CrSpec {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
217impl crate::Readable for CrSpec {}
218#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
219impl crate::Writable for CrSpec {
220    type Safety = crate::Unsafe;
221}
222#[doc = "`reset()` method sets CR to value 0x80"]
223impl crate::Resettable for CrSpec {
224    const RESET_VALUE: u32 = 0x80;
225}
mcxa_pac/rtc0/cr.rs

mcxa_pac/rtc0/
cr.rs
