1#[doc = "Register `PCR0` reader"]
2pub type R = crate::R<Pcr0Spec>;
3#[doc = "Register `PCR0` writer"]
4pub type W = crate::W<Pcr0Spec>;
5#[doc = "Pull Select\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Ps {
9 #[doc = "0: Enables internal pulldown resistor"]
10 Ps0 = 0,
11 #[doc = "1: Enables internal pullup resistor"]
12 Ps1 = 1,
13}
14impl From<Ps> for bool {
15 #[inline(always)]
16 fn from(variant: Ps) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `PS` reader - Pull Select"]
21pub type PsR = crate::BitReader<Ps>;
22impl PsR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Ps {
26 match self.bits {
27 false => Ps::Ps0,
28 true => Ps::Ps1,
29 }
30 }
31 #[doc = "Enables internal pulldown resistor"]
32 #[inline(always)]
33 pub fn is_ps0(&self) -> bool {
34 *self == Ps::Ps0
35 }
36 #[doc = "Enables internal pullup resistor"]
37 #[inline(always)]
38 pub fn is_ps1(&self) -> bool {
39 *self == Ps::Ps1
40 }
41}
42#[doc = "Field `PS` writer - Pull Select"]
43pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>;
44impl<'a, REG> PsW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Enables internal pulldown resistor"]
49 #[inline(always)]
50 pub fn ps0(self) -> &'a mut crate::W<REG> {
51 self.variant(Ps::Ps0)
52 }
53 #[doc = "Enables internal pullup resistor"]
54 #[inline(always)]
55 pub fn ps1(self) -> &'a mut crate::W<REG> {
56 self.variant(Ps::Ps1)
57 }
58}
59#[doc = "Pull Enable\n\nValue on reset: 1"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Pe {
63 #[doc = "0: Disables"]
64 Pe0 = 0,
65 #[doc = "1: Enables"]
66 Pe1 = 1,
67}
68impl From<Pe> for bool {
69 #[inline(always)]
70 fn from(variant: Pe) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `PE` reader - Pull Enable"]
75pub type PeR = crate::BitReader<Pe>;
76impl PeR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Pe {
80 match self.bits {
81 false => Pe::Pe0,
82 true => Pe::Pe1,
83 }
84 }
85 #[doc = "Disables"]
86 #[inline(always)]
87 pub fn is_pe0(&self) -> bool {
88 *self == Pe::Pe0
89 }
90 #[doc = "Enables"]
91 #[inline(always)]
92 pub fn is_pe1(&self) -> bool {
93 *self == Pe::Pe1
94 }
95}
96#[doc = "Field `PE` writer - Pull Enable"]
97pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>;
98impl<'a, REG> PeW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Disables"]
103 #[inline(always)]
104 pub fn pe0(self) -> &'a mut crate::W<REG> {
105 self.variant(Pe::Pe0)
106 }
107 #[doc = "Enables"]
108 #[inline(always)]
109 pub fn pe1(self) -> &'a mut crate::W<REG> {
110 self.variant(Pe::Pe1)
111 }
112}
113#[doc = "Slew Rate Enable\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Sre {
117 #[doc = "0: Fast"]
118 Sre0 = 0,
119 #[doc = "1: Slow"]
120 Sre1 = 1,
121}
122impl From<Sre> for bool {
123 #[inline(always)]
124 fn from(variant: Sre) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `SRE` reader - Slew Rate Enable"]
129pub type SreR = crate::BitReader<Sre>;
130impl SreR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Sre {
134 match self.bits {
135 false => Sre::Sre0,
136 true => Sre::Sre1,
137 }
138 }
139 #[doc = "Fast"]
140 #[inline(always)]
141 pub fn is_sre0(&self) -> bool {
142 *self == Sre::Sre0
143 }
144 #[doc = "Slow"]
145 #[inline(always)]
146 pub fn is_sre1(&self) -> bool {
147 *self == Sre::Sre1
148 }
149}
150#[doc = "Field `SRE` writer - Slew Rate Enable"]
151pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>;
152impl<'a, REG> SreW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "Fast"]
157 #[inline(always)]
158 pub fn sre0(self) -> &'a mut crate::W<REG> {
159 self.variant(Sre::Sre0)
160 }
161 #[doc = "Slow"]
162 #[inline(always)]
163 pub fn sre1(self) -> &'a mut crate::W<REG> {
164 self.variant(Sre::Sre1)
165 }
166}
167#[doc = "Open Drain Enable\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Ode {
171 #[doc = "0: Disables"]
172 Ode0 = 0,
173 #[doc = "1: Enables"]
174 Ode1 = 1,
175}
176impl From<Ode> for bool {
177 #[inline(always)]
178 fn from(variant: Ode) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `ODE` reader - Open Drain Enable"]
183pub type OdeR = crate::BitReader<Ode>;
184impl OdeR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> Ode {
188 match self.bits {
189 false => Ode::Ode0,
190 true => Ode::Ode1,
191 }
192 }
193 #[doc = "Disables"]
194 #[inline(always)]
195 pub fn is_ode0(&self) -> bool {
196 *self == Ode::Ode0
197 }
198 #[doc = "Enables"]
199 #[inline(always)]
200 pub fn is_ode1(&self) -> bool {
201 *self == Ode::Ode1
202 }
203}
204#[doc = "Field `ODE` writer - Open Drain Enable"]
205pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>;
206impl<'a, REG> OdeW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Disables"]
211 #[inline(always)]
212 pub fn ode0(self) -> &'a mut crate::W<REG> {
213 self.variant(Ode::Ode0)
214 }
215 #[doc = "Enables"]
216 #[inline(always)]
217 pub fn ode1(self) -> &'a mut crate::W<REG> {
218 self.variant(Ode::Ode1)
219 }
220}
221#[doc = "Drive Strength Enable\n\nValue on reset: 1"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Dse {
225 #[doc = "0: Low"]
226 Dse0 = 0,
227 #[doc = "1: High"]
228 Dse1 = 1,
229}
230impl From<Dse> for bool {
231 #[inline(always)]
232 fn from(variant: Dse) -> Self {
233 variant as u8 != 0
234 }
235}
236#[doc = "Field `DSE` reader - Drive Strength Enable"]
237pub type DseR = crate::BitReader<Dse>;
238impl DseR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> Dse {
242 match self.bits {
243 false => Dse::Dse0,
244 true => Dse::Dse1,
245 }
246 }
247 #[doc = "Low"]
248 #[inline(always)]
249 pub fn is_dse0(&self) -> bool {
250 *self == Dse::Dse0
251 }
252 #[doc = "High"]
253 #[inline(always)]
254 pub fn is_dse1(&self) -> bool {
255 *self == Dse::Dse1
256 }
257}
258#[doc = "Field `DSE` writer - Drive Strength Enable"]
259pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>;
260impl<'a, REG> DseW<'a, REG>
261where
262 REG: crate::Writable + crate::RegisterSpec,
263{
264 #[doc = "Low"]
265 #[inline(always)]
266 pub fn dse0(self) -> &'a mut crate::W<REG> {
267 self.variant(Dse::Dse0)
268 }
269 #[doc = "High"]
270 #[inline(always)]
271 pub fn dse1(self) -> &'a mut crate::W<REG> {
272 self.variant(Dse::Dse1)
273 }
274}
275#[doc = "Pin Multiplex Control\n\nValue on reset: 1"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278#[repr(u8)]
279pub enum Mux {
280 #[doc = "0: Alternative 0 (typically GPIO)"]
281 Mux0 = 0,
282 #[doc = "1: Alternative 1 (Pin/Port Dependent)"]
283 Mux1 = 1,
284 #[doc = "2: Alternative 2 (Pin/Port Dependent)"]
285 Mux2 = 2,
286 #[doc = "3: Alternative 3 (Pin/Port Dependent)"]
287 Mux3 = 3,
288 #[doc = "4: Alternative 4 (Pin/Port Dependent)"]
289 Mux4 = 4,
290 #[doc = "5: Alternative 5 (Pin/Port Dependent)"]
291 Mux5 = 5,
292 #[doc = "6: Alternative 6 (Pin/Port Dependent)"]
293 Mux6 = 6,
294 #[doc = "7: Alternative 7 (Pin/Port Dependent)"]
295 Mux7 = 7,
296 #[doc = "8: Alternative 8 (Pin/Port Dependent)"]
297 Mux8 = 8,
298 #[doc = "9: Alternative 9 (Pin/Port Dependent)"]
299 Mux9 = 9,
300 #[doc = "10: Alternative 10 (Pin/Port Dependent)"]
301 Mux10 = 10,
302 #[doc = "11: Alternative 11 (Pin/Port Dependent)"]
303 Mux11 = 11,
304 #[doc = "12: Alternative 12 (Pin/Port Dependent)"]
305 Mux12 = 12,
306 #[doc = "13: Alternative 13 (Pin/Port Dependent)"]
307 Mux13 = 13,
308 #[doc = "14: Alternative 14 (Pin/Port Dependent)"]
309 Mux14 = 14,
310 #[doc = "15: Alternative 15 (Pin/Port Dependent)"]
311 Mux15 = 15,
312}
313impl From<Mux> for u8 {
314 #[inline(always)]
315 fn from(variant: Mux) -> Self {
316 variant as _
317 }
318}
319impl crate::FieldSpec for Mux {
320 type Ux = u8;
321}
322impl crate::IsEnum for Mux {}
323#[doc = "Field `MUX` reader - Pin Multiplex Control"]
324pub type MuxR = crate::FieldReader<Mux>;
325impl MuxR {
326 #[doc = "Get enumerated values variant"]
327 #[inline(always)]
328 pub const fn variant(&self) -> Mux {
329 match self.bits {
330 0 => Mux::Mux0,
331 1 => Mux::Mux1,
332 2 => Mux::Mux2,
333 3 => Mux::Mux3,
334 4 => Mux::Mux4,
335 5 => Mux::Mux5,
336 6 => Mux::Mux6,
337 7 => Mux::Mux7,
338 8 => Mux::Mux8,
339 9 => Mux::Mux9,
340 10 => Mux::Mux10,
341 11 => Mux::Mux11,
342 12 => Mux::Mux12,
343 13 => Mux::Mux13,
344 14 => Mux::Mux14,
345 15 => Mux::Mux15,
346 _ => unreachable!(),
347 }
348 }
349 #[doc = "Alternative 0 (typically GPIO)"]
350 #[inline(always)]
351 pub fn is_mux0(&self) -> bool {
352 *self == Mux::Mux0
353 }
354 #[doc = "Alternative 1 (Pin/Port Dependent)"]
355 #[inline(always)]
356 pub fn is_mux1(&self) -> bool {
357 *self == Mux::Mux1
358 }
359 #[doc = "Alternative 2 (Pin/Port Dependent)"]
360 #[inline(always)]
361 pub fn is_mux2(&self) -> bool {
362 *self == Mux::Mux2
363 }
364 #[doc = "Alternative 3 (Pin/Port Dependent)"]
365 #[inline(always)]
366 pub fn is_mux3(&self) -> bool {
367 *self == Mux::Mux3
368 }
369 #[doc = "Alternative 4 (Pin/Port Dependent)"]
370 #[inline(always)]
371 pub fn is_mux4(&self) -> bool {
372 *self == Mux::Mux4
373 }
374 #[doc = "Alternative 5 (Pin/Port Dependent)"]
375 #[inline(always)]
376 pub fn is_mux5(&self) -> bool {
377 *self == Mux::Mux5
378 }
379 #[doc = "Alternative 6 (Pin/Port Dependent)"]
380 #[inline(always)]
381 pub fn is_mux6(&self) -> bool {
382 *self == Mux::Mux6
383 }
384 #[doc = "Alternative 7 (Pin/Port Dependent)"]
385 #[inline(always)]
386 pub fn is_mux7(&self) -> bool {
387 *self == Mux::Mux7
388 }
389 #[doc = "Alternative 8 (Pin/Port Dependent)"]
390 #[inline(always)]
391 pub fn is_mux8(&self) -> bool {
392 *self == Mux::Mux8
393 }
394 #[doc = "Alternative 9 (Pin/Port Dependent)"]
395 #[inline(always)]
396 pub fn is_mux9(&self) -> bool {
397 *self == Mux::Mux9
398 }
399 #[doc = "Alternative 10 (Pin/Port Dependent)"]
400 #[inline(always)]
401 pub fn is_mux10(&self) -> bool {
402 *self == Mux::Mux10
403 }
404 #[doc = "Alternative 11 (Pin/Port Dependent)"]
405 #[inline(always)]
406 pub fn is_mux11(&self) -> bool {
407 *self == Mux::Mux11
408 }
409 #[doc = "Alternative 12 (Pin/Port Dependent)"]
410 #[inline(always)]
411 pub fn is_mux12(&self) -> bool {
412 *self == Mux::Mux12
413 }
414 #[doc = "Alternative 13 (Pin/Port Dependent)"]
415 #[inline(always)]
416 pub fn is_mux13(&self) -> bool {
417 *self == Mux::Mux13
418 }
419 #[doc = "Alternative 14 (Pin/Port Dependent)"]
420 #[inline(always)]
421 pub fn is_mux14(&self) -> bool {
422 *self == Mux::Mux14
423 }
424 #[doc = "Alternative 15 (Pin/Port Dependent)"]
425 #[inline(always)]
426 pub fn is_mux15(&self) -> bool {
427 *self == Mux::Mux15
428 }
429}
430#[doc = "Field `MUX` writer - Pin Multiplex Control"]
431pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux, crate::Safe>;
432impl<'a, REG> MuxW<'a, REG>
433where
434 REG: crate::Writable + crate::RegisterSpec,
435 REG::Ux: From<u8>,
436{
437 #[doc = "Alternative 0 (typically GPIO)"]
438 #[inline(always)]
439 pub fn mux0(self) -> &'a mut crate::W<REG> {
440 self.variant(Mux::Mux0)
441 }
442 #[doc = "Alternative 1 (Pin/Port Dependent)"]
443 #[inline(always)]
444 pub fn mux1(self) -> &'a mut crate::W<REG> {
445 self.variant(Mux::Mux1)
446 }
447 #[doc = "Alternative 2 (Pin/Port Dependent)"]
448 #[inline(always)]
449 pub fn mux2(self) -> &'a mut crate::W<REG> {
450 self.variant(Mux::Mux2)
451 }
452 #[doc = "Alternative 3 (Pin/Port Dependent)"]
453 #[inline(always)]
454 pub fn mux3(self) -> &'a mut crate::W<REG> {
455 self.variant(Mux::Mux3)
456 }
457 #[doc = "Alternative 4 (Pin/Port Dependent)"]
458 #[inline(always)]
459 pub fn mux4(self) -> &'a mut crate::W<REG> {
460 self.variant(Mux::Mux4)
461 }
462 #[doc = "Alternative 5 (Pin/Port Dependent)"]
463 #[inline(always)]
464 pub fn mux5(self) -> &'a mut crate::W<REG> {
465 self.variant(Mux::Mux5)
466 }
467 #[doc = "Alternative 6 (Pin/Port Dependent)"]
468 #[inline(always)]
469 pub fn mux6(self) -> &'a mut crate::W<REG> {
470 self.variant(Mux::Mux6)
471 }
472 #[doc = "Alternative 7 (Pin/Port Dependent)"]
473 #[inline(always)]
474 pub fn mux7(self) -> &'a mut crate::W<REG> {
475 self.variant(Mux::Mux7)
476 }
477 #[doc = "Alternative 8 (Pin/Port Dependent)"]
478 #[inline(always)]
479 pub fn mux8(self) -> &'a mut crate::W<REG> {
480 self.variant(Mux::Mux8)
481 }
482 #[doc = "Alternative 9 (Pin/Port Dependent)"]
483 #[inline(always)]
484 pub fn mux9(self) -> &'a mut crate::W<REG> {
485 self.variant(Mux::Mux9)
486 }
487 #[doc = "Alternative 10 (Pin/Port Dependent)"]
488 #[inline(always)]
489 pub fn mux10(self) -> &'a mut crate::W<REG> {
490 self.variant(Mux::Mux10)
491 }
492 #[doc = "Alternative 11 (Pin/Port Dependent)"]
493 #[inline(always)]
494 pub fn mux11(self) -> &'a mut crate::W<REG> {
495 self.variant(Mux::Mux11)
496 }
497 #[doc = "Alternative 12 (Pin/Port Dependent)"]
498 #[inline(always)]
499 pub fn mux12(self) -> &'a mut crate::W<REG> {
500 self.variant(Mux::Mux12)
501 }
502 #[doc = "Alternative 13 (Pin/Port Dependent)"]
503 #[inline(always)]
504 pub fn mux13(self) -> &'a mut crate::W<REG> {
505 self.variant(Mux::Mux13)
506 }
507 #[doc = "Alternative 14 (Pin/Port Dependent)"]
508 #[inline(always)]
509 pub fn mux14(self) -> &'a mut crate::W<REG> {
510 self.variant(Mux::Mux14)
511 }
512 #[doc = "Alternative 15 (Pin/Port Dependent)"]
513 #[inline(always)]
514 pub fn mux15(self) -> &'a mut crate::W<REG> {
515 self.variant(Mux::Mux15)
516 }
517}
518#[doc = "Input Buffer Enable\n\nValue on reset: 1"]
519#[cfg_attr(feature = "defmt", derive(defmt::Format))]
520#[derive(Clone, Copy, Debug, PartialEq, Eq)]
521pub enum Ibe {
522 #[doc = "0: Disables"]
523 Ibe0 = 0,
524 #[doc = "1: Enables"]
525 Ibe1 = 1,
526}
527impl From<Ibe> for bool {
528 #[inline(always)]
529 fn from(variant: Ibe) -> Self {
530 variant as u8 != 0
531 }
532}
533#[doc = "Field `IBE` reader - Input Buffer Enable"]
534pub type IbeR = crate::BitReader<Ibe>;
535impl IbeR {
536 #[doc = "Get enumerated values variant"]
537 #[inline(always)]
538 pub const fn variant(&self) -> Ibe {
539 match self.bits {
540 false => Ibe::Ibe0,
541 true => Ibe::Ibe1,
542 }
543 }
544 #[doc = "Disables"]
545 #[inline(always)]
546 pub fn is_ibe0(&self) -> bool {
547 *self == Ibe::Ibe0
548 }
549 #[doc = "Enables"]
550 #[inline(always)]
551 pub fn is_ibe1(&self) -> bool {
552 *self == Ibe::Ibe1
553 }
554}
555#[doc = "Field `IBE` writer - Input Buffer Enable"]
556pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>;
557impl<'a, REG> IbeW<'a, REG>
558where
559 REG: crate::Writable + crate::RegisterSpec,
560{
561 #[doc = "Disables"]
562 #[inline(always)]
563 pub fn ibe0(self) -> &'a mut crate::W<REG> {
564 self.variant(Ibe::Ibe0)
565 }
566 #[doc = "Enables"]
567 #[inline(always)]
568 pub fn ibe1(self) -> &'a mut crate::W<REG> {
569 self.variant(Ibe::Ibe1)
570 }
571}
572#[doc = "Invert Input\n\nValue on reset: 0"]
573#[cfg_attr(feature = "defmt", derive(defmt::Format))]
574#[derive(Clone, Copy, Debug, PartialEq, Eq)]
575pub enum Inv {
576 #[doc = "0: Does not invert"]
577 Inv0 = 0,
578 #[doc = "1: Inverts"]
579 Inv1 = 1,
580}
581impl From<Inv> for bool {
582 #[inline(always)]
583 fn from(variant: Inv) -> Self {
584 variant as u8 != 0
585 }
586}
587#[doc = "Field `INV` reader - Invert Input"]
588pub type InvR = crate::BitReader<Inv>;
589impl InvR {
590 #[doc = "Get enumerated values variant"]
591 #[inline(always)]
592 pub const fn variant(&self) -> Inv {
593 match self.bits {
594 false => Inv::Inv0,
595 true => Inv::Inv1,
596 }
597 }
598 #[doc = "Does not invert"]
599 #[inline(always)]
600 pub fn is_inv0(&self) -> bool {
601 *self == Inv::Inv0
602 }
603 #[doc = "Inverts"]
604 #[inline(always)]
605 pub fn is_inv1(&self) -> bool {
606 *self == Inv::Inv1
607 }
608}
609#[doc = "Field `INV` writer - Invert Input"]
610pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>;
611impl<'a, REG> InvW<'a, REG>
612where
613 REG: crate::Writable + crate::RegisterSpec,
614{
615 #[doc = "Does not invert"]
616 #[inline(always)]
617 pub fn inv0(self) -> &'a mut crate::W<REG> {
618 self.variant(Inv::Inv0)
619 }
620 #[doc = "Inverts"]
621 #[inline(always)]
622 pub fn inv1(self) -> &'a mut crate::W<REG> {
623 self.variant(Inv::Inv1)
624 }
625}
626#[doc = "Lock Register\n\nValue on reset: 0"]
627#[cfg_attr(feature = "defmt", derive(defmt::Format))]
628#[derive(Clone, Copy, Debug, PartialEq, Eq)]
629pub enum Lk {
630 #[doc = "0: Does not lock"]
631 Lk0 = 0,
632 #[doc = "1: Locks"]
633 Lk1 = 1,
634}
635impl From<Lk> for bool {
636 #[inline(always)]
637 fn from(variant: Lk) -> Self {
638 variant as u8 != 0
639 }
640}
641#[doc = "Field `LK` reader - Lock Register"]
642pub type LkR = crate::BitReader<Lk>;
643impl LkR {
644 #[doc = "Get enumerated values variant"]
645 #[inline(always)]
646 pub const fn variant(&self) -> Lk {
647 match self.bits {
648 false => Lk::Lk0,
649 true => Lk::Lk1,
650 }
651 }
652 #[doc = "Does not lock"]
653 #[inline(always)]
654 pub fn is_lk0(&self) -> bool {
655 *self == Lk::Lk0
656 }
657 #[doc = "Locks"]
658 #[inline(always)]
659 pub fn is_lk1(&self) -> bool {
660 *self == Lk::Lk1
661 }
662}
663#[doc = "Field `LK` writer - Lock Register"]
664pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>;
665impl<'a, REG> LkW<'a, REG>
666where
667 REG: crate::Writable + crate::RegisterSpec,
668{
669 #[doc = "Does not lock"]
670 #[inline(always)]
671 pub fn lk0(self) -> &'a mut crate::W<REG> {
672 self.variant(Lk::Lk0)
673 }
674 #[doc = "Locks"]
675 #[inline(always)]
676 pub fn lk1(self) -> &'a mut crate::W<REG> {
677 self.variant(Lk::Lk1)
678 }
679}
680impl R {
681 #[doc = "Bit 0 - Pull Select"]
682 #[inline(always)]
683 pub fn ps(&self) -> PsR {
684 PsR::new((self.bits & 1) != 0)
685 }
686 #[doc = "Bit 1 - Pull Enable"]
687 #[inline(always)]
688 pub fn pe(&self) -> PeR {
689 PeR::new(((self.bits >> 1) & 1) != 0)
690 }
691 #[doc = "Bit 3 - Slew Rate Enable"]
692 #[inline(always)]
693 pub fn sre(&self) -> SreR {
694 SreR::new(((self.bits >> 3) & 1) != 0)
695 }
696 #[doc = "Bit 5 - Open Drain Enable"]
697 #[inline(always)]
698 pub fn ode(&self) -> OdeR {
699 OdeR::new(((self.bits >> 5) & 1) != 0)
700 }
701 #[doc = "Bit 6 - Drive Strength Enable"]
702 #[inline(always)]
703 pub fn dse(&self) -> DseR {
704 DseR::new(((self.bits >> 6) & 1) != 0)
705 }
706 #[doc = "Bits 8:11 - Pin Multiplex Control"]
707 #[inline(always)]
708 pub fn mux(&self) -> MuxR {
709 MuxR::new(((self.bits >> 8) & 0x0f) as u8)
710 }
711 #[doc = "Bit 12 - Input Buffer Enable"]
712 #[inline(always)]
713 pub fn ibe(&self) -> IbeR {
714 IbeR::new(((self.bits >> 12) & 1) != 0)
715 }
716 #[doc = "Bit 13 - Invert Input"]
717 #[inline(always)]
718 pub fn inv(&self) -> InvR {
719 InvR::new(((self.bits >> 13) & 1) != 0)
720 }
721 #[doc = "Bit 15 - Lock Register"]
722 #[inline(always)]
723 pub fn lk(&self) -> LkR {
724 LkR::new(((self.bits >> 15) & 1) != 0)
725 }
726}
727#[cfg(feature = "debug")]
728impl core::fmt::Debug for R {
729 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
730 f.debug_struct("PCR0")
731 .field("ps", &self.ps())
732 .field("pe", &self.pe())
733 .field("sre", &self.sre())
734 .field("ode", &self.ode())
735 .field("dse", &self.dse())
736 .field("mux", &self.mux())
737 .field("ibe", &self.ibe())
738 .field("inv", &self.inv())
739 .field("lk", &self.lk())
740 .finish()
741 }
742}
743impl W {
744 #[doc = "Bit 0 - Pull Select"]
745 #[inline(always)]
746 pub fn ps(&mut self) -> PsW<'_, Pcr0Spec> {
747 PsW::new(self, 0)
748 }
749 #[doc = "Bit 1 - Pull Enable"]
750 #[inline(always)]
751 pub fn pe(&mut self) -> PeW<'_, Pcr0Spec> {
752 PeW::new(self, 1)
753 }
754 #[doc = "Bit 3 - Slew Rate Enable"]
755 #[inline(always)]
756 pub fn sre(&mut self) -> SreW<'_, Pcr0Spec> {
757 SreW::new(self, 3)
758 }
759 #[doc = "Bit 5 - Open Drain Enable"]
760 #[inline(always)]
761 pub fn ode(&mut self) -> OdeW<'_, Pcr0Spec> {
762 OdeW::new(self, 5)
763 }
764 #[doc = "Bit 6 - Drive Strength Enable"]
765 #[inline(always)]
766 pub fn dse(&mut self) -> DseW<'_, Pcr0Spec> {
767 DseW::new(self, 6)
768 }
769 #[doc = "Bits 8:11 - Pin Multiplex Control"]
770 #[inline(always)]
771 pub fn mux(&mut self) -> MuxW<'_, Pcr0Spec> {
772 MuxW::new(self, 8)
773 }
774 #[doc = "Bit 12 - Input Buffer Enable"]
775 #[inline(always)]
776 pub fn ibe(&mut self) -> IbeW<'_, Pcr0Spec> {
777 IbeW::new(self, 12)
778 }
779 #[doc = "Bit 13 - Invert Input"]
780 #[inline(always)]
781 pub fn inv(&mut self) -> InvW<'_, Pcr0Spec> {
782 InvW::new(self, 13)
783 }
784 #[doc = "Bit 15 - Lock Register"]
785 #[inline(always)]
786 pub fn lk(&mut self) -> LkW<'_, Pcr0Spec> {
787 LkW::new(self, 15)
788 }
789}
790#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
791pub struct Pcr0Spec;
792impl crate::RegisterSpec for Pcr0Spec {
793 type Ux = u32;
794}
795#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"]
796impl crate::Readable for Pcr0Spec {}
797#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"]
798impl crate::Writable for Pcr0Spec {
799 type Safety = crate::Unsafe;
800}
801#[doc = "`reset()` method sets PCR0 to value 0x1143"]
802impl crate::Resettable for Pcr0Spec {
803 const RESET_VALUE: u32 = 0x1143;
804}