mcxa_pac/pkc0/
pkc_int_clr_enable.rs

1#[doc = "Register `PKC_INT_CLR_ENABLE` writer"]
2pub type W = crate::W<PkcIntClrEnableSpec>;
3#[doc = "Field `EN_PDONE` writer - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=0)."]
4pub type EnPdoneW<'a, REG> = crate::BitWriter<'a, REG>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<PkcIntClrEnableSpec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bit 0 - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=0)."]
13    #[inline(always)]
14    pub fn en_pdone(&mut self) -> EnPdoneW<'_, PkcIntClrEnableSpec> {
15        EnPdoneW::new(self, 0)
16    }
17}
18#[doc = "Interrupt enable clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_enable::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct PkcIntClrEnableSpec;
20impl crate::RegisterSpec for PkcIntClrEnableSpec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`pkc_int_clr_enable::W`](W) writer structure"]
24impl crate::Writable for PkcIntClrEnableSpec {
25    type Safety = crate::Unsafe;
26}
27#[doc = "`reset()` method sets PKC_INT_CLR_ENABLE to value 0"]
28impl crate::Resettable for PkcIntClrEnableSpec {}
mcxa_pac/pkc0/pkc_int_clr_enable.rs

mcxa_pac/pkc0/
pkc_int_clr_enable.rs
