mcxa_pac/mrcc0/
mrcc_ostimer0_clksel.rs

1#[doc = "Register `MRCC_OSTIMER0_CLKSEL` reader"]
2pub type R = crate::R<MrccOstimer0ClkselSpec>;
3#[doc = "Register `MRCC_OSTIMER0_CLKSEL` writer"]
4pub type W = crate::W<MrccOstimer0ClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "0: CLK_16K"]
11    Clkroot16k = 0,
12    #[doc = "2: CLK_1M"]
13    Clkroot1m = 2,
14}
15impl From<Mux> for u8 {
16    #[inline(always)]
17    fn from(variant: Mux) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Mux {
22    type Ux = u8;
23}
24impl crate::IsEnum for Mux {}
25#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
26pub type MuxR = crate::FieldReader<Mux>;
27impl MuxR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Mux> {
31        match self.bits {
32            0 => Some(Mux::Clkroot16k),
33            2 => Some(Mux::Clkroot1m),
34            _ => None,
35        }
36    }
37    #[doc = "CLK_16K"]
38    #[inline(always)]
39    pub fn is_clkroot_16k(&self) -> bool {
40        *self == Mux::Clkroot16k
41    }
42    #[doc = "CLK_1M"]
43    #[inline(always)]
44    pub fn is_clkroot_1m(&self) -> bool {
45        *self == Mux::Clkroot1m
46    }
47}
48#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
49pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>;
50impl<'a, REG> MuxW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u8>,
54{
55    #[doc = "CLK_16K"]
56    #[inline(always)]
57    pub fn clkroot_16k(self) -> &'a mut crate::W<REG> {
58        self.variant(Mux::Clkroot16k)
59    }
60    #[doc = "CLK_1M"]
61    #[inline(always)]
62    pub fn clkroot_1m(self) -> &'a mut crate::W<REG> {
63        self.variant(Mux::Clkroot1m)
64    }
65}
66impl R {
67    #[doc = "Bits 0:1 - Functional Clock Mux Select"]
68    #[inline(always)]
69    pub fn mux(&self) -> MuxR {
70        MuxR::new((self.bits & 3) as u8)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("MRCC_OSTIMER0_CLKSEL")
77            .field("mux", &self.mux())
78            .finish()
79    }
80}
81impl W {
82    #[doc = "Bits 0:1 - Functional Clock Mux Select"]
83    #[inline(always)]
84    pub fn mux(&mut self) -> MuxW<'_, MrccOstimer0ClkselSpec> {
85        MuxW::new(self, 0)
86    }
87}
88#[doc = "OSTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ostimer0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ostimer0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct MrccOstimer0ClkselSpec;
90impl crate::RegisterSpec for MrccOstimer0ClkselSpec {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`mrcc_ostimer0_clksel::R`](R) reader structure"]
94impl crate::Readable for MrccOstimer0ClkselSpec {}
95#[doc = "`write(|w| ..)` method takes [`mrcc_ostimer0_clksel::W`](W) writer structure"]
96impl crate::Writable for MrccOstimer0ClkselSpec {
97    type Safety = crate::Unsafe;
98}
99#[doc = "`reset()` method sets MRCC_OSTIMER0_CLKSEL to value 0x03"]
100impl crate::Resettable for MrccOstimer0ClkselSpec {
101    const RESET_VALUE: u32 = 0x03;
102}
mcxa_pac/mrcc0/mrcc_ostimer0_clksel.rs

mcxa_pac/mrcc0/
mrcc_ostimer0_clksel.rs
