mcxa_pac/mrcc0/
mrcc_flexio0_clksel.rs

1#[doc = "Register `MRCC_FLEXIO0_CLKSEL` reader"]
2pub type R = crate::R<MrccFlexio0ClkselSpec>;
3#[doc = "Register `MRCC_FLEXIO0_CLKSEL` writer"]
4pub type W = crate::W<MrccFlexio0ClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "0: FRO_LF_DIV"]
11    ClkrootFunc0 = 0,
12    #[doc = "1: FRO_HF_GATED"]
13    ClkrootFunc1 = 1,
14    #[doc = "3: CLK_IN"]
15    ClkrootFunc3 = 3,
16    #[doc = "5: CLK_1M"]
17    ClkrootFunc5 = 5,
18    #[doc = "6: PLL1_CLK_DIV"]
19    ClkrootFunc6 = 6,
20}
21impl From<Mux> for u8 {
22    #[inline(always)]
23    fn from(variant: Mux) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for Mux {
28    type Ux = u8;
29}
30impl crate::IsEnum for Mux {}
31#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
32pub type MuxR = crate::FieldReader<Mux>;
33impl MuxR {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<Mux> {
37        match self.bits {
38            0 => Some(Mux::ClkrootFunc0),
39            1 => Some(Mux::ClkrootFunc1),
40            3 => Some(Mux::ClkrootFunc3),
41            5 => Some(Mux::ClkrootFunc5),
42            6 => Some(Mux::ClkrootFunc6),
43            _ => None,
44        }
45    }
46    #[doc = "FRO_LF_DIV"]
47    #[inline(always)]
48    pub fn is_clkroot_func_0(&self) -> bool {
49        *self == Mux::ClkrootFunc0
50    }
51    #[doc = "FRO_HF_GATED"]
52    #[inline(always)]
53    pub fn is_clkroot_func_1(&self) -> bool {
54        *self == Mux::ClkrootFunc1
55    }
56    #[doc = "CLK_IN"]
57    #[inline(always)]
58    pub fn is_clkroot_func_3(&self) -> bool {
59        *self == Mux::ClkrootFunc3
60    }
61    #[doc = "CLK_1M"]
62    #[inline(always)]
63    pub fn is_clkroot_func_5(&self) -> bool {
64        *self == Mux::ClkrootFunc5
65    }
66    #[doc = "PLL1_CLK_DIV"]
67    #[inline(always)]
68    pub fn is_clkroot_func_6(&self) -> bool {
69        *self == Mux::ClkrootFunc6
70    }
71}
72#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
73pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>;
74impl<'a, REG> MuxW<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77    REG::Ux: From<u8>,
78{
79    #[doc = "FRO_LF_DIV"]
80    #[inline(always)]
81    pub fn clkroot_func_0(self) -> &'a mut crate::W<REG> {
82        self.variant(Mux::ClkrootFunc0)
83    }
84    #[doc = "FRO_HF_GATED"]
85    #[inline(always)]
86    pub fn clkroot_func_1(self) -> &'a mut crate::W<REG> {
87        self.variant(Mux::ClkrootFunc1)
88    }
89    #[doc = "CLK_IN"]
90    #[inline(always)]
91    pub fn clkroot_func_3(self) -> &'a mut crate::W<REG> {
92        self.variant(Mux::ClkrootFunc3)
93    }
94    #[doc = "CLK_1M"]
95    #[inline(always)]
96    pub fn clkroot_func_5(self) -> &'a mut crate::W<REG> {
97        self.variant(Mux::ClkrootFunc5)
98    }
99    #[doc = "PLL1_CLK_DIV"]
100    #[inline(always)]
101    pub fn clkroot_func_6(self) -> &'a mut crate::W<REG> {
102        self.variant(Mux::ClkrootFunc6)
103    }
104}
105impl R {
106    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
107    #[inline(always)]
108    pub fn mux(&self) -> MuxR {
109        MuxR::new((self.bits & 7) as u8)
110    }
111}
112#[cfg(feature = "debug")]
113impl core::fmt::Debug for R {
114    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
115        f.debug_struct("MRCC_FLEXIO0_CLKSEL").field("mux", &self.mux()).finish()
116    }
117}
118impl W {
119    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
120    #[inline(always)]
121    pub fn mux(&mut self) -> MuxW<'_, MrccFlexio0ClkselSpec> {
122        MuxW::new(self, 0)
123    }
124}
125#[doc = "FLEXIO0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
126pub struct MrccFlexio0ClkselSpec;
127impl crate::RegisterSpec for MrccFlexio0ClkselSpec {
128    type Ux = u32;
129}
130#[doc = "`read()` method returns [`mrcc_flexio0_clksel::R`](R) reader structure"]
131impl crate::Readable for MrccFlexio0ClkselSpec {}
132#[doc = "`write(|w| ..)` method takes [`mrcc_flexio0_clksel::W`](W) writer structure"]
133impl crate::Writable for MrccFlexio0ClkselSpec {
134    type Safety = crate::Unsafe;
135}
136#[doc = "`reset()` method sets MRCC_FLEXIO0_CLKSEL to value 0x07"]
137impl crate::Resettable for MrccFlexio0ClkselSpec {
138    const RESET_VALUE: u32 = 0x07;
139}
mcxa_pac/mrcc0/mrcc_flexio0_clksel.rs

mcxa_pac/mrcc0/
mrcc_flexio0_clksel.rs
