mcxa_pac/mrcc0/
mrcc_flexcan0_clksel.rs

1#[doc = "Register `MRCC_FLEXCAN0_CLKSEL` reader"]
2pub type R = crate::R<MrccFlexcan0ClkselSpec>;
3#[doc = "Register `MRCC_FLEXCAN0_CLKSEL` writer"]
4pub type W = crate::W<MrccFlexcan0ClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "1: FRO_HF_GATED"]
11    ClkrootFircGated = 1,
12    #[doc = "2: FRO_HF_DIV"]
13    ClkrootFircDiv = 2,
14    #[doc = "3: CLK_IN"]
15    ClkrootSosc = 3,
16    #[doc = "6: PLL1_CLK"]
17    ClkrootSpll = 6,
18}
19impl From<Mux> for u8 {
20    #[inline(always)]
21    fn from(variant: Mux) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for Mux {
26    type Ux = u8;
27}
28impl crate::IsEnum for Mux {}
29#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
30pub type MuxR = crate::FieldReader<Mux>;
31impl MuxR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<Mux> {
35        match self.bits {
36            1 => Some(Mux::ClkrootFircGated),
37            2 => Some(Mux::ClkrootFircDiv),
38            3 => Some(Mux::ClkrootSosc),
39            6 => Some(Mux::ClkrootSpll),
40            _ => None,
41        }
42    }
43    #[doc = "FRO_HF_GATED"]
44    #[inline(always)]
45    pub fn is_clkroot_firc_gated(&self) -> bool {
46        *self == Mux::ClkrootFircGated
47    }
48    #[doc = "FRO_HF_DIV"]
49    #[inline(always)]
50    pub fn is_clkroot_firc_div(&self) -> bool {
51        *self == Mux::ClkrootFircDiv
52    }
53    #[doc = "CLK_IN"]
54    #[inline(always)]
55    pub fn is_clkroot_sosc(&self) -> bool {
56        *self == Mux::ClkrootSosc
57    }
58    #[doc = "PLL1_CLK"]
59    #[inline(always)]
60    pub fn is_clkroot_spll(&self) -> bool {
61        *self == Mux::ClkrootSpll
62    }
63}
64#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
65pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>;
66impl<'a, REG> MuxW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "FRO_HF_GATED"]
72    #[inline(always)]
73    pub fn clkroot_firc_gated(self) -> &'a mut crate::W<REG> {
74        self.variant(Mux::ClkrootFircGated)
75    }
76    #[doc = "FRO_HF_DIV"]
77    #[inline(always)]
78    pub fn clkroot_firc_div(self) -> &'a mut crate::W<REG> {
79        self.variant(Mux::ClkrootFircDiv)
80    }
81    #[doc = "CLK_IN"]
82    #[inline(always)]
83    pub fn clkroot_sosc(self) -> &'a mut crate::W<REG> {
84        self.variant(Mux::ClkrootSosc)
85    }
86    #[doc = "PLL1_CLK"]
87    #[inline(always)]
88    pub fn clkroot_spll(self) -> &'a mut crate::W<REG> {
89        self.variant(Mux::ClkrootSpll)
90    }
91}
92impl R {
93    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
94    #[inline(always)]
95    pub fn mux(&self) -> MuxR {
96        MuxR::new((self.bits & 7) as u8)
97    }
98}
99#[cfg(feature = "debug")]
100impl core::fmt::Debug for R {
101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102        f.debug_struct("MRCC_FLEXCAN0_CLKSEL")
103            .field("mux", &self.mux())
104            .finish()
105    }
106}
107impl W {
108    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
109    #[inline(always)]
110    pub fn mux(&mut self) -> MuxW<'_, MrccFlexcan0ClkselSpec> {
111        MuxW::new(self, 0)
112    }
113}
114#[doc = "FLEXCAN0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct MrccFlexcan0ClkselSpec;
116impl crate::RegisterSpec for MrccFlexcan0ClkselSpec {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`mrcc_flexcan0_clksel::R`](R) reader structure"]
120impl crate::Readable for MrccFlexcan0ClkselSpec {}
121#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan0_clksel::W`](W) writer structure"]
122impl crate::Writable for MrccFlexcan0ClkselSpec {
123    type Safety = crate::Unsafe;
124}
125#[doc = "`reset()` method sets MRCC_FLEXCAN0_CLKSEL to value 0x07"]
126impl crate::Resettable for MrccFlexcan0ClkselSpec {
127    const RESET_VALUE: u32 = 0x07;
128}
mcxa_pac/mrcc0/mrcc_flexcan0_clksel.rs

mcxa_pac/mrcc0/
mrcc_flexcan0_clksel.rs
