mcxa_pac/mrcc0/
mrcc_clkout_clksel.rs

1#[doc = "Register `MRCC_CLKOUT_CLKSEL` reader"]
2pub type R = crate::R<MrccClkoutClkselSpec>;
3#[doc = "Register `MRCC_CLKOUT_CLKSEL` writer"]
4pub type W = crate::W<MrccClkoutClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "0: FRO_12M"]
11    Clkroot12m = 0,
12    #[doc = "1: FRO_HF_DIV"]
13    ClkrootFircDiv = 1,
14    #[doc = "2: CLK_IN"]
15    ClkrootSosc = 2,
16    #[doc = "3: CLK_16K"]
17    Clkroot16k = 3,
18    #[doc = "5: PLL1_CLK"]
19    ClkrootSpll = 5,
20    #[doc = "6: SLOW_CLK"]
21    ClkrootSlow = 6,
22}
23impl From<Mux> for u8 {
24    #[inline(always)]
25    fn from(variant: Mux) -> Self {
26        variant as _
27    }
28}
29impl crate::FieldSpec for Mux {
30    type Ux = u8;
31}
32impl crate::IsEnum for Mux {}
33#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
34pub type MuxR = crate::FieldReader<Mux>;
35impl MuxR {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<Mux> {
39        match self.bits {
40            0 => Some(Mux::Clkroot12m),
41            1 => Some(Mux::ClkrootFircDiv),
42            2 => Some(Mux::ClkrootSosc),
43            3 => Some(Mux::Clkroot16k),
44            5 => Some(Mux::ClkrootSpll),
45            6 => Some(Mux::ClkrootSlow),
46            _ => None,
47        }
48    }
49    #[doc = "FRO_12M"]
50    #[inline(always)]
51    pub fn is_clkroot_12m(&self) -> bool {
52        *self == Mux::Clkroot12m
53    }
54    #[doc = "FRO_HF_DIV"]
55    #[inline(always)]
56    pub fn is_clkroot_firc_div(&self) -> bool {
57        *self == Mux::ClkrootFircDiv
58    }
59    #[doc = "CLK_IN"]
60    #[inline(always)]
61    pub fn is_clkroot_sosc(&self) -> bool {
62        *self == Mux::ClkrootSosc
63    }
64    #[doc = "CLK_16K"]
65    #[inline(always)]
66    pub fn is_clkroot_16k(&self) -> bool {
67        *self == Mux::Clkroot16k
68    }
69    #[doc = "PLL1_CLK"]
70    #[inline(always)]
71    pub fn is_clkroot_spll(&self) -> bool {
72        *self == Mux::ClkrootSpll
73    }
74    #[doc = "SLOW_CLK"]
75    #[inline(always)]
76    pub fn is_clkroot_slow(&self) -> bool {
77        *self == Mux::ClkrootSlow
78    }
79}
80#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
81pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>;
82impl<'a, REG> MuxW<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "FRO_12M"]
88    #[inline(always)]
89    pub fn clkroot_12m(self) -> &'a mut crate::W<REG> {
90        self.variant(Mux::Clkroot12m)
91    }
92    #[doc = "FRO_HF_DIV"]
93    #[inline(always)]
94    pub fn clkroot_firc_div(self) -> &'a mut crate::W<REG> {
95        self.variant(Mux::ClkrootFircDiv)
96    }
97    #[doc = "CLK_IN"]
98    #[inline(always)]
99    pub fn clkroot_sosc(self) -> &'a mut crate::W<REG> {
100        self.variant(Mux::ClkrootSosc)
101    }
102    #[doc = "CLK_16K"]
103    #[inline(always)]
104    pub fn clkroot_16k(self) -> &'a mut crate::W<REG> {
105        self.variant(Mux::Clkroot16k)
106    }
107    #[doc = "PLL1_CLK"]
108    #[inline(always)]
109    pub fn clkroot_spll(self) -> &'a mut crate::W<REG> {
110        self.variant(Mux::ClkrootSpll)
111    }
112    #[doc = "SLOW_CLK"]
113    #[inline(always)]
114    pub fn clkroot_slow(self) -> &'a mut crate::W<REG> {
115        self.variant(Mux::ClkrootSlow)
116    }
117}
118impl R {
119    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
120    #[inline(always)]
121    pub fn mux(&self) -> MuxR {
122        MuxR::new((self.bits & 7) as u8)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("MRCC_CLKOUT_CLKSEL").field("mux", &self.mux()).finish()
129    }
130}
131impl W {
132    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
133    #[inline(always)]
134    pub fn mux(&mut self) -> MuxW<'_, MrccClkoutClkselSpec> {
135        MuxW::new(self, 0)
136    }
137}
138#[doc = "CLKOUT clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
139pub struct MrccClkoutClkselSpec;
140impl crate::RegisterSpec for MrccClkoutClkselSpec {
141    type Ux = u32;
142}
143#[doc = "`read()` method returns [`mrcc_clkout_clksel::R`](R) reader structure"]
144impl crate::Readable for MrccClkoutClkselSpec {}
145#[doc = "`write(|w| ..)` method takes [`mrcc_clkout_clksel::W`](W) writer structure"]
146impl crate::Writable for MrccClkoutClkselSpec {
147    type Safety = crate::Unsafe;
148}
149#[doc = "`reset()` method sets MRCC_CLKOUT_CLKSEL to value 0x07"]
150impl crate::Resettable for MrccClkoutClkselSpec {
151    const RESET_VALUE: u32 = 0x07;
152}
mcxa_pac/mrcc0/mrcc_clkout_clksel.rs

mcxa_pac/mrcc0/
mrcc_clkout_clksel.rs
