mcxa_pac/lpuart0/
pincfg.rs

1#[doc = "Register `PINCFG` reader"]
2pub type R = crate::R<PincfgSpec>;
3#[doc = "Register `PINCFG` writer"]
4pub type W = crate::W<PincfgSpec>;
5#[doc = "Trigger Select\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Trgsel {
10    #[doc = "0: Input trigger disabled"]
11    Disabled = 0,
12    #[doc = "1: Input trigger used instead of the RXD pin input"]
13    TrgRxd = 1,
14    #[doc = "2: Input trigger used instead of the CTS_B pin input"]
15    TrgCts = 2,
16    #[doc = "3: Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"]
17    TrgTxd = 3,
18}
19impl From<Trgsel> for u8 {
20    #[inline(always)]
21    fn from(variant: Trgsel) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for Trgsel {
26    type Ux = u8;
27}
28impl crate::IsEnum for Trgsel {}
29#[doc = "Field `TRGSEL` reader - Trigger Select"]
30pub type TrgselR = crate::FieldReader<Trgsel>;
31impl TrgselR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Trgsel {
35        match self.bits {
36            0 => Trgsel::Disabled,
37            1 => Trgsel::TrgRxd,
38            2 => Trgsel::TrgCts,
39            3 => Trgsel::TrgTxd,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "Input trigger disabled"]
44    #[inline(always)]
45    pub fn is_disabled(&self) -> bool {
46        *self == Trgsel::Disabled
47    }
48    #[doc = "Input trigger used instead of the RXD pin input"]
49    #[inline(always)]
50    pub fn is_trg_rxd(&self) -> bool {
51        *self == Trgsel::TrgRxd
52    }
53    #[doc = "Input trigger used instead of the CTS_B pin input"]
54    #[inline(always)]
55    pub fn is_trg_cts(&self) -> bool {
56        *self == Trgsel::TrgCts
57    }
58    #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"]
59    #[inline(always)]
60    pub fn is_trg_txd(&self) -> bool {
61        *self == Trgsel::TrgTxd
62    }
63}
64#[doc = "Field `TRGSEL` writer - Trigger Select"]
65pub type TrgselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trgsel, crate::Safe>;
66impl<'a, REG> TrgselW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "Input trigger disabled"]
72    #[inline(always)]
73    pub fn disabled(self) -> &'a mut crate::W<REG> {
74        self.variant(Trgsel::Disabled)
75    }
76    #[doc = "Input trigger used instead of the RXD pin input"]
77    #[inline(always)]
78    pub fn trg_rxd(self) -> &'a mut crate::W<REG> {
79        self.variant(Trgsel::TrgRxd)
80    }
81    #[doc = "Input trigger used instead of the CTS_B pin input"]
82    #[inline(always)]
83    pub fn trg_cts(self) -> &'a mut crate::W<REG> {
84        self.variant(Trgsel::TrgCts)
85    }
86    #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"]
87    #[inline(always)]
88    pub fn trg_txd(self) -> &'a mut crate::W<REG> {
89        self.variant(Trgsel::TrgTxd)
90    }
91}
92impl R {
93    #[doc = "Bits 0:1 - Trigger Select"]
94    #[inline(always)]
95    pub fn trgsel(&self) -> TrgselR {
96        TrgselR::new((self.bits & 3) as u8)
97    }
98}
99#[cfg(feature = "debug")]
100impl core::fmt::Debug for R {
101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102        f.debug_struct("PINCFG").field("trgsel", &self.trgsel()).finish()
103    }
104}
105impl W {
106    #[doc = "Bits 0:1 - Trigger Select"]
107    #[inline(always)]
108    pub fn trgsel(&mut self) -> TrgselW<'_, PincfgSpec> {
109        TrgselW::new(self, 0)
110    }
111}
112#[doc = "Pin Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pincfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pincfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
113pub struct PincfgSpec;
114impl crate::RegisterSpec for PincfgSpec {
115    type Ux = u32;
116}
117#[doc = "`read()` method returns [`pincfg::R`](R) reader structure"]
118impl crate::Readable for PincfgSpec {}
119#[doc = "`write(|w| ..)` method takes [`pincfg::W`](W) writer structure"]
120impl crate::Writable for PincfgSpec {
121    type Safety = crate::Unsafe;
122}
123#[doc = "`reset()` method sets PINCFG to value 0"]
124impl crate::Resettable for PincfgSpec {}
mcxa_pac/lpuart0/pincfg.rs

mcxa_pac/lpuart0/
pincfg.rs
