1#[doc = "Register `PSR` reader"]
2pub type R = crate::R<PsrSpec>;
3#[doc = "Register `PSR` writer"]
4pub type W = crate::W<PsrSpec>;
5#[doc = "Prescaler and Glitch Filter Clock Select\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Pcs {
10 #[doc = "0: Clock 0"]
11 Pcs00 = 0,
12 #[doc = "1: Clock 1"]
13 Pcs01 = 1,
14 #[doc = "2: Clock 2"]
15 Pcs10 = 2,
16 #[doc = "3: Clock 3"]
17 Pcs11 = 3,
18}
19impl From<Pcs> for u8 {
20 #[inline(always)]
21 fn from(variant: Pcs) -> Self {
22 variant as _
23 }
24}
25impl crate::FieldSpec for Pcs {
26 type Ux = u8;
27}
28impl crate::IsEnum for Pcs {}
29#[doc = "Field `PCS` reader - Prescaler and Glitch Filter Clock Select"]
30pub type PcsR = crate::FieldReader<Pcs>;
31impl PcsR {
32 #[doc = "Get enumerated values variant"]
33 #[inline(always)]
34 pub const fn variant(&self) -> Pcs {
35 match self.bits {
36 0 => Pcs::Pcs00,
37 1 => Pcs::Pcs01,
38 2 => Pcs::Pcs10,
39 3 => Pcs::Pcs11,
40 _ => unreachable!(),
41 }
42 }
43 #[doc = "Clock 0"]
44 #[inline(always)]
45 pub fn is_pcs00(&self) -> bool {
46 *self == Pcs::Pcs00
47 }
48 #[doc = "Clock 1"]
49 #[inline(always)]
50 pub fn is_pcs01(&self) -> bool {
51 *self == Pcs::Pcs01
52 }
53 #[doc = "Clock 2"]
54 #[inline(always)]
55 pub fn is_pcs10(&self) -> bool {
56 *self == Pcs::Pcs10
57 }
58 #[doc = "Clock 3"]
59 #[inline(always)]
60 pub fn is_pcs11(&self) -> bool {
61 *self == Pcs::Pcs11
62 }
63}
64#[doc = "Field `PCS` writer - Prescaler and Glitch Filter Clock Select"]
65pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pcs, crate::Safe>;
66impl<'a, REG> PcsW<'a, REG>
67where
68 REG: crate::Writable + crate::RegisterSpec,
69 REG::Ux: From<u8>,
70{
71 #[doc = "Clock 0"]
72 #[inline(always)]
73 pub fn pcs00(self) -> &'a mut crate::W<REG> {
74 self.variant(Pcs::Pcs00)
75 }
76 #[doc = "Clock 1"]
77 #[inline(always)]
78 pub fn pcs01(self) -> &'a mut crate::W<REG> {
79 self.variant(Pcs::Pcs01)
80 }
81 #[doc = "Clock 2"]
82 #[inline(always)]
83 pub fn pcs10(self) -> &'a mut crate::W<REG> {
84 self.variant(Pcs::Pcs10)
85 }
86 #[doc = "Clock 3"]
87 #[inline(always)]
88 pub fn pcs11(self) -> &'a mut crate::W<REG> {
89 self.variant(Pcs::Pcs11)
90 }
91}
92#[doc = "Prescaler and Glitch Filter Bypass\n\nValue on reset: 0"]
93#[cfg_attr(feature = "defmt", derive(defmt::Format))]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum Pbyp {
96 #[doc = "0: Prescaler and glitch filter enable"]
97 Pbyp0 = 0,
98 #[doc = "1: Prescaler and glitch filter bypass"]
99 Pbyp1 = 1,
100}
101impl From<Pbyp> for bool {
102 #[inline(always)]
103 fn from(variant: Pbyp) -> Self {
104 variant as u8 != 0
105 }
106}
107#[doc = "Field `PBYP` reader - Prescaler and Glitch Filter Bypass"]
108pub type PbypR = crate::BitReader<Pbyp>;
109impl PbypR {
110 #[doc = "Get enumerated values variant"]
111 #[inline(always)]
112 pub const fn variant(&self) -> Pbyp {
113 match self.bits {
114 false => Pbyp::Pbyp0,
115 true => Pbyp::Pbyp1,
116 }
117 }
118 #[doc = "Prescaler and glitch filter enable"]
119 #[inline(always)]
120 pub fn is_pbyp0(&self) -> bool {
121 *self == Pbyp::Pbyp0
122 }
123 #[doc = "Prescaler and glitch filter bypass"]
124 #[inline(always)]
125 pub fn is_pbyp1(&self) -> bool {
126 *self == Pbyp::Pbyp1
127 }
128}
129#[doc = "Field `PBYP` writer - Prescaler and Glitch Filter Bypass"]
130pub type PbypW<'a, REG> = crate::BitWriter<'a, REG, Pbyp>;
131impl<'a, REG> PbypW<'a, REG>
132where
133 REG: crate::Writable + crate::RegisterSpec,
134{
135 #[doc = "Prescaler and glitch filter enable"]
136 #[inline(always)]
137 pub fn pbyp0(self) -> &'a mut crate::W<REG> {
138 self.variant(Pbyp::Pbyp0)
139 }
140 #[doc = "Prescaler and glitch filter bypass"]
141 #[inline(always)]
142 pub fn pbyp1(self) -> &'a mut crate::W<REG> {
143 self.variant(Pbyp::Pbyp1)
144 }
145}
146#[doc = "Prescaler and Glitch Filter Value\n\nValue on reset: 0"]
147#[cfg_attr(feature = "defmt", derive(defmt::Format))]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149#[repr(u8)]
150pub enum Prescale {
151 #[doc = "0: Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"]
152 Prescale0000 = 0,
153 #[doc = "1: Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"]
154 Prescale0001 = 1,
155 #[doc = "2: Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"]
156 Prescale0010 = 2,
157 #[doc = "3: Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"]
158 Prescale0011 = 3,
159 #[doc = "4: Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"]
160 Prescale0100 = 4,
161 #[doc = "5: Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"]
162 Prescale0101 = 5,
163 #[doc = "6: Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"]
164 Prescale0110 = 6,
165 #[doc = "7: Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"]
166 Prescale0111 = 7,
167 #[doc = "8: Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"]
168 Prescale1000 = 8,
169 #[doc = "9: Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"]
170 Prescale1001 = 9,
171 #[doc = "10: Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"]
172 Prescale1010 = 10,
173 #[doc = "11: Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"]
174 Prescale1011 = 11,
175 #[doc = "12: Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"]
176 Prescale1100 = 12,
177 #[doc = "13: Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"]
178 Prescale1101 = 13,
179 #[doc = "14: Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"]
180 Prescale1110 = 14,
181 #[doc = "15: Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"]
182 Prescale1111 = 15,
183}
184impl From<Prescale> for u8 {
185 #[inline(always)]
186 fn from(variant: Prescale) -> Self {
187 variant as _
188 }
189}
190impl crate::FieldSpec for Prescale {
191 type Ux = u8;
192}
193impl crate::IsEnum for Prescale {}
194#[doc = "Field `PRESCALE` reader - Prescaler and Glitch Filter Value"]
195pub type PrescaleR = crate::FieldReader<Prescale>;
196impl PrescaleR {
197 #[doc = "Get enumerated values variant"]
198 #[inline(always)]
199 pub const fn variant(&self) -> Prescale {
200 match self.bits {
201 0 => Prescale::Prescale0000,
202 1 => Prescale::Prescale0001,
203 2 => Prescale::Prescale0010,
204 3 => Prescale::Prescale0011,
205 4 => Prescale::Prescale0100,
206 5 => Prescale::Prescale0101,
207 6 => Prescale::Prescale0110,
208 7 => Prescale::Prescale0111,
209 8 => Prescale::Prescale1000,
210 9 => Prescale::Prescale1001,
211 10 => Prescale::Prescale1010,
212 11 => Prescale::Prescale1011,
213 12 => Prescale::Prescale1100,
214 13 => Prescale::Prescale1101,
215 14 => Prescale::Prescale1110,
216 15 => Prescale::Prescale1111,
217 _ => unreachable!(),
218 }
219 }
220 #[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"]
221 #[inline(always)]
222 pub fn is_prescale0000(&self) -> bool {
223 *self == Prescale::Prescale0000
224 }
225 #[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"]
226 #[inline(always)]
227 pub fn is_prescale0001(&self) -> bool {
228 *self == Prescale::Prescale0001
229 }
230 #[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"]
231 #[inline(always)]
232 pub fn is_prescale0010(&self) -> bool {
233 *self == Prescale::Prescale0010
234 }
235 #[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"]
236 #[inline(always)]
237 pub fn is_prescale0011(&self) -> bool {
238 *self == Prescale::Prescale0011
239 }
240 #[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"]
241 #[inline(always)]
242 pub fn is_prescale0100(&self) -> bool {
243 *self == Prescale::Prescale0100
244 }
245 #[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"]
246 #[inline(always)]
247 pub fn is_prescale0101(&self) -> bool {
248 *self == Prescale::Prescale0101
249 }
250 #[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"]
251 #[inline(always)]
252 pub fn is_prescale0110(&self) -> bool {
253 *self == Prescale::Prescale0110
254 }
255 #[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"]
256 #[inline(always)]
257 pub fn is_prescale0111(&self) -> bool {
258 *self == Prescale::Prescale0111
259 }
260 #[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"]
261 #[inline(always)]
262 pub fn is_prescale1000(&self) -> bool {
263 *self == Prescale::Prescale1000
264 }
265 #[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"]
266 #[inline(always)]
267 pub fn is_prescale1001(&self) -> bool {
268 *self == Prescale::Prescale1001
269 }
270 #[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"]
271 #[inline(always)]
272 pub fn is_prescale1010(&self) -> bool {
273 *self == Prescale::Prescale1010
274 }
275 #[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"]
276 #[inline(always)]
277 pub fn is_prescale1011(&self) -> bool {
278 *self == Prescale::Prescale1011
279 }
280 #[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"]
281 #[inline(always)]
282 pub fn is_prescale1100(&self) -> bool {
283 *self == Prescale::Prescale1100
284 }
285 #[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"]
286 #[inline(always)]
287 pub fn is_prescale1101(&self) -> bool {
288 *self == Prescale::Prescale1101
289 }
290 #[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"]
291 #[inline(always)]
292 pub fn is_prescale1110(&self) -> bool {
293 *self == Prescale::Prescale1110
294 }
295 #[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"]
296 #[inline(always)]
297 pub fn is_prescale1111(&self) -> bool {
298 *self == Prescale::Prescale1111
299 }
300}
301#[doc = "Field `PRESCALE` writer - Prescaler and Glitch Filter Value"]
302pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescale, crate::Safe>;
303impl<'a, REG> PrescaleW<'a, REG>
304where
305 REG: crate::Writable + crate::RegisterSpec,
306 REG::Ux: From<u8>,
307{
308 #[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"]
309 #[inline(always)]
310 pub fn prescale0000(self) -> &'a mut crate::W<REG> {
311 self.variant(Prescale::Prescale0000)
312 }
313 #[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"]
314 #[inline(always)]
315 pub fn prescale0001(self) -> &'a mut crate::W<REG> {
316 self.variant(Prescale::Prescale0001)
317 }
318 #[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"]
319 #[inline(always)]
320 pub fn prescale0010(self) -> &'a mut crate::W<REG> {
321 self.variant(Prescale::Prescale0010)
322 }
323 #[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"]
324 #[inline(always)]
325 pub fn prescale0011(self) -> &'a mut crate::W<REG> {
326 self.variant(Prescale::Prescale0011)
327 }
328 #[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"]
329 #[inline(always)]
330 pub fn prescale0100(self) -> &'a mut crate::W<REG> {
331 self.variant(Prescale::Prescale0100)
332 }
333 #[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"]
334 #[inline(always)]
335 pub fn prescale0101(self) -> &'a mut crate::W<REG> {
336 self.variant(Prescale::Prescale0101)
337 }
338 #[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"]
339 #[inline(always)]
340 pub fn prescale0110(self) -> &'a mut crate::W<REG> {
341 self.variant(Prescale::Prescale0110)
342 }
343 #[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"]
344 #[inline(always)]
345 pub fn prescale0111(self) -> &'a mut crate::W<REG> {
346 self.variant(Prescale::Prescale0111)
347 }
348 #[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"]
349 #[inline(always)]
350 pub fn prescale1000(self) -> &'a mut crate::W<REG> {
351 self.variant(Prescale::Prescale1000)
352 }
353 #[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"]
354 #[inline(always)]
355 pub fn prescale1001(self) -> &'a mut crate::W<REG> {
356 self.variant(Prescale::Prescale1001)
357 }
358 #[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"]
359 #[inline(always)]
360 pub fn prescale1010(self) -> &'a mut crate::W<REG> {
361 self.variant(Prescale::Prescale1010)
362 }
363 #[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"]
364 #[inline(always)]
365 pub fn prescale1011(self) -> &'a mut crate::W<REG> {
366 self.variant(Prescale::Prescale1011)
367 }
368 #[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"]
369 #[inline(always)]
370 pub fn prescale1100(self) -> &'a mut crate::W<REG> {
371 self.variant(Prescale::Prescale1100)
372 }
373 #[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"]
374 #[inline(always)]
375 pub fn prescale1101(self) -> &'a mut crate::W<REG> {
376 self.variant(Prescale::Prescale1101)
377 }
378 #[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"]
379 #[inline(always)]
380 pub fn prescale1110(self) -> &'a mut crate::W<REG> {
381 self.variant(Prescale::Prescale1110)
382 }
383 #[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"]
384 #[inline(always)]
385 pub fn prescale1111(self) -> &'a mut crate::W<REG> {
386 self.variant(Prescale::Prescale1111)
387 }
388}
389impl R {
390 #[doc = "Bits 0:1 - Prescaler and Glitch Filter Clock Select"]
391 #[inline(always)]
392 pub fn pcs(&self) -> PcsR {
393 PcsR::new((self.bits & 3) as u8)
394 }
395 #[doc = "Bit 2 - Prescaler and Glitch Filter Bypass"]
396 #[inline(always)]
397 pub fn pbyp(&self) -> PbypR {
398 PbypR::new(((self.bits >> 2) & 1) != 0)
399 }
400 #[doc = "Bits 3:6 - Prescaler and Glitch Filter Value"]
401 #[inline(always)]
402 pub fn prescale(&self) -> PrescaleR {
403 PrescaleR::new(((self.bits >> 3) & 0x0f) as u8)
404 }
405}
406#[cfg(feature = "debug")]
407impl core::fmt::Debug for R {
408 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
409 f.debug_struct("PSR")
410 .field("pcs", &self.pcs())
411 .field("pbyp", &self.pbyp())
412 .field("prescale", &self.prescale())
413 .finish()
414 }
415}
416impl W {
417 #[doc = "Bits 0:1 - Prescaler and Glitch Filter Clock Select"]
418 #[inline(always)]
419 pub fn pcs(&mut self) -> PcsW<'_, PsrSpec> {
420 PcsW::new(self, 0)
421 }
422 #[doc = "Bit 2 - Prescaler and Glitch Filter Bypass"]
423 #[inline(always)]
424 pub fn pbyp(&mut self) -> PbypW<'_, PsrSpec> {
425 PbypW::new(self, 2)
426 }
427 #[doc = "Bits 3:6 - Prescaler and Glitch Filter Value"]
428 #[inline(always)]
429 pub fn prescale(&mut self) -> PrescaleW<'_, PsrSpec> {
430 PrescaleW::new(self, 3)
431 }
432}
433#[doc = "Prescaler and Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
434pub struct PsrSpec;
435impl crate::RegisterSpec for PsrSpec {
436 type Ux = u32;
437}
438#[doc = "`read()` method returns [`psr::R`](R) reader structure"]
439impl crate::Readable for PsrSpec {}
440#[doc = "`write(|w| ..)` method takes [`psr::W`](W) writer structure"]
441impl crate::Writable for PsrSpec {
442 type Safety = crate::Unsafe;
443}
444#[doc = "`reset()` method sets PSR to value 0"]
445impl crate::Resettable for PsrSpec {}