mcxa_pac/lpspi0/
tcr.rs

1#[doc = "Register `TCR` reader"]
2pub type R = crate::R<TcrSpec>;
3#[doc = "Register `TCR` writer"]
4pub type W = crate::W<TcrSpec>;
5#[doc = "Field `FRAMESZ` reader - Frame Size"]
6pub type FrameszR = crate::FieldReader<u16>;
7#[doc = "Field `FRAMESZ` writer - Frame Size"]
8pub type FrameszW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Transfer Width\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12#[repr(u8)]
13pub enum Width {
14    #[doc = "0: 1-bit transfer"]
15    Onebit = 0,
16    #[doc = "1: 2-bit transfer"]
17    Twobit = 1,
18    #[doc = "2: 4-bit transfer"]
19    Fourbit = 2,
20}
21impl From<Width> for u8 {
22    #[inline(always)]
23    fn from(variant: Width) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for Width {
28    type Ux = u8;
29}
30impl crate::IsEnum for Width {}
31#[doc = "Field `WIDTH` reader - Transfer Width"]
32pub type WidthR = crate::FieldReader<Width>;
33impl WidthR {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<Width> {
37        match self.bits {
38            0 => Some(Width::Onebit),
39            1 => Some(Width::Twobit),
40            2 => Some(Width::Fourbit),
41            _ => None,
42        }
43    }
44    #[doc = "1-bit transfer"]
45    #[inline(always)]
46    pub fn is_onebit(&self) -> bool {
47        *self == Width::Onebit
48    }
49    #[doc = "2-bit transfer"]
50    #[inline(always)]
51    pub fn is_twobit(&self) -> bool {
52        *self == Width::Twobit
53    }
54    #[doc = "4-bit transfer"]
55    #[inline(always)]
56    pub fn is_fourbit(&self) -> bool {
57        *self == Width::Fourbit
58    }
59}
60#[doc = "Field `WIDTH` writer - Transfer Width"]
61pub type WidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Width>;
62impl<'a, REG> WidthW<'a, REG>
63where
64    REG: crate::Writable + crate::RegisterSpec,
65    REG::Ux: From<u8>,
66{
67    #[doc = "1-bit transfer"]
68    #[inline(always)]
69    pub fn onebit(self) -> &'a mut crate::W<REG> {
70        self.variant(Width::Onebit)
71    }
72    #[doc = "2-bit transfer"]
73    #[inline(always)]
74    pub fn twobit(self) -> &'a mut crate::W<REG> {
75        self.variant(Width::Twobit)
76    }
77    #[doc = "4-bit transfer"]
78    #[inline(always)]
79    pub fn fourbit(self) -> &'a mut crate::W<REG> {
80        self.variant(Width::Fourbit)
81    }
82}
83#[doc = "Transmit Data Mask\n\nValue on reset: 0"]
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum Txmsk {
87    #[doc = "0: Normal transfer"]
88    Normal = 0,
89    #[doc = "1: Mask transmit data"]
90    Mask = 1,
91}
92impl From<Txmsk> for bool {
93    #[inline(always)]
94    fn from(variant: Txmsk) -> Self {
95        variant as u8 != 0
96    }
97}
98#[doc = "Field `TXMSK` reader - Transmit Data Mask"]
99pub type TxmskR = crate::BitReader<Txmsk>;
100impl TxmskR {
101    #[doc = "Get enumerated values variant"]
102    #[inline(always)]
103    pub const fn variant(&self) -> Txmsk {
104        match self.bits {
105            false => Txmsk::Normal,
106            true => Txmsk::Mask,
107        }
108    }
109    #[doc = "Normal transfer"]
110    #[inline(always)]
111    pub fn is_normal(&self) -> bool {
112        *self == Txmsk::Normal
113    }
114    #[doc = "Mask transmit data"]
115    #[inline(always)]
116    pub fn is_mask(&self) -> bool {
117        *self == Txmsk::Mask
118    }
119}
120#[doc = "Field `TXMSK` writer - Transmit Data Mask"]
121pub type TxmskW<'a, REG> = crate::BitWriter<'a, REG, Txmsk>;
122impl<'a, REG> TxmskW<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125{
126    #[doc = "Normal transfer"]
127    #[inline(always)]
128    pub fn normal(self) -> &'a mut crate::W<REG> {
129        self.variant(Txmsk::Normal)
130    }
131    #[doc = "Mask transmit data"]
132    #[inline(always)]
133    pub fn mask(self) -> &'a mut crate::W<REG> {
134        self.variant(Txmsk::Mask)
135    }
136}
137#[doc = "Receive Data Mask\n\nValue on reset: 0"]
138#[cfg_attr(feature = "defmt", derive(defmt::Format))]
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140pub enum Rxmsk {
141    #[doc = "0: Normal transfer"]
142    Normal = 0,
143    #[doc = "1: Mask receive data"]
144    Mask = 1,
145}
146impl From<Rxmsk> for bool {
147    #[inline(always)]
148    fn from(variant: Rxmsk) -> Self {
149        variant as u8 != 0
150    }
151}
152#[doc = "Field `RXMSK` reader - Receive Data Mask"]
153pub type RxmskR = crate::BitReader<Rxmsk>;
154impl RxmskR {
155    #[doc = "Get enumerated values variant"]
156    #[inline(always)]
157    pub const fn variant(&self) -> Rxmsk {
158        match self.bits {
159            false => Rxmsk::Normal,
160            true => Rxmsk::Mask,
161        }
162    }
163    #[doc = "Normal transfer"]
164    #[inline(always)]
165    pub fn is_normal(&self) -> bool {
166        *self == Rxmsk::Normal
167    }
168    #[doc = "Mask receive data"]
169    #[inline(always)]
170    pub fn is_mask(&self) -> bool {
171        *self == Rxmsk::Mask
172    }
173}
174#[doc = "Field `RXMSK` writer - Receive Data Mask"]
175pub type RxmskW<'a, REG> = crate::BitWriter<'a, REG, Rxmsk>;
176impl<'a, REG> RxmskW<'a, REG>
177where
178    REG: crate::Writable + crate::RegisterSpec,
179{
180    #[doc = "Normal transfer"]
181    #[inline(always)]
182    pub fn normal(self) -> &'a mut crate::W<REG> {
183        self.variant(Rxmsk::Normal)
184    }
185    #[doc = "Mask receive data"]
186    #[inline(always)]
187    pub fn mask(self) -> &'a mut crate::W<REG> {
188        self.variant(Rxmsk::Mask)
189    }
190}
191#[doc = "Continuing Command\n\nValue on reset: 0"]
192#[cfg_attr(feature = "defmt", derive(defmt::Format))]
193#[derive(Clone, Copy, Debug, PartialEq, Eq)]
194pub enum Contc {
195    #[doc = "0: Command word for start of new transfer"]
196    Start = 0,
197    #[doc = "1: Command word for continuing transfer"]
198    Continue = 1,
199}
200impl From<Contc> for bool {
201    #[inline(always)]
202    fn from(variant: Contc) -> Self {
203        variant as u8 != 0
204    }
205}
206#[doc = "Field `CONTC` reader - Continuing Command"]
207pub type ContcR = crate::BitReader<Contc>;
208impl ContcR {
209    #[doc = "Get enumerated values variant"]
210    #[inline(always)]
211    pub const fn variant(&self) -> Contc {
212        match self.bits {
213            false => Contc::Start,
214            true => Contc::Continue,
215        }
216    }
217    #[doc = "Command word for start of new transfer"]
218    #[inline(always)]
219    pub fn is_start(&self) -> bool {
220        *self == Contc::Start
221    }
222    #[doc = "Command word for continuing transfer"]
223    #[inline(always)]
224    pub fn is_continue(&self) -> bool {
225        *self == Contc::Continue
226    }
227}
228#[doc = "Field `CONTC` writer - Continuing Command"]
229pub type ContcW<'a, REG> = crate::BitWriter<'a, REG, Contc>;
230impl<'a, REG> ContcW<'a, REG>
231where
232    REG: crate::Writable + crate::RegisterSpec,
233{
234    #[doc = "Command word for start of new transfer"]
235    #[inline(always)]
236    pub fn start(self) -> &'a mut crate::W<REG> {
237        self.variant(Contc::Start)
238    }
239    #[doc = "Command word for continuing transfer"]
240    #[inline(always)]
241    pub fn continue_(self) -> &'a mut crate::W<REG> {
242        self.variant(Contc::Continue)
243    }
244}
245#[doc = "Continuous Transfer\n\nValue on reset: 0"]
246#[cfg_attr(feature = "defmt", derive(defmt::Format))]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248pub enum Cont {
249    #[doc = "0: Disable"]
250    Disabled = 0,
251    #[doc = "1: Enable"]
252    Enabled = 1,
253}
254impl From<Cont> for bool {
255    #[inline(always)]
256    fn from(variant: Cont) -> Self {
257        variant as u8 != 0
258    }
259}
260#[doc = "Field `CONT` reader - Continuous Transfer"]
261pub type ContR = crate::BitReader<Cont>;
262impl ContR {
263    #[doc = "Get enumerated values variant"]
264    #[inline(always)]
265    pub const fn variant(&self) -> Cont {
266        match self.bits {
267            false => Cont::Disabled,
268            true => Cont::Enabled,
269        }
270    }
271    #[doc = "Disable"]
272    #[inline(always)]
273    pub fn is_disabled(&self) -> bool {
274        *self == Cont::Disabled
275    }
276    #[doc = "Enable"]
277    #[inline(always)]
278    pub fn is_enabled(&self) -> bool {
279        *self == Cont::Enabled
280    }
281}
282#[doc = "Field `CONT` writer - Continuous Transfer"]
283pub type ContW<'a, REG> = crate::BitWriter<'a, REG, Cont>;
284impl<'a, REG> ContW<'a, REG>
285where
286    REG: crate::Writable + crate::RegisterSpec,
287{
288    #[doc = "Disable"]
289    #[inline(always)]
290    pub fn disabled(self) -> &'a mut crate::W<REG> {
291        self.variant(Cont::Disabled)
292    }
293    #[doc = "Enable"]
294    #[inline(always)]
295    pub fn enabled(self) -> &'a mut crate::W<REG> {
296        self.variant(Cont::Enabled)
297    }
298}
299#[doc = "Byte Swap\n\nValue on reset: 0"]
300#[cfg_attr(feature = "defmt", derive(defmt::Format))]
301#[derive(Clone, Copy, Debug, PartialEq, Eq)]
302pub enum Bysw {
303    #[doc = "0: Disable byte swap"]
304    Disabled = 0,
305    #[doc = "1: Enable byte swap"]
306    Enabled = 1,
307}
308impl From<Bysw> for bool {
309    #[inline(always)]
310    fn from(variant: Bysw) -> Self {
311        variant as u8 != 0
312    }
313}
314#[doc = "Field `BYSW` reader - Byte Swap"]
315pub type ByswR = crate::BitReader<Bysw>;
316impl ByswR {
317    #[doc = "Get enumerated values variant"]
318    #[inline(always)]
319    pub const fn variant(&self) -> Bysw {
320        match self.bits {
321            false => Bysw::Disabled,
322            true => Bysw::Enabled,
323        }
324    }
325    #[doc = "Disable byte swap"]
326    #[inline(always)]
327    pub fn is_disabled(&self) -> bool {
328        *self == Bysw::Disabled
329    }
330    #[doc = "Enable byte swap"]
331    #[inline(always)]
332    pub fn is_enabled(&self) -> bool {
333        *self == Bysw::Enabled
334    }
335}
336#[doc = "Field `BYSW` writer - Byte Swap"]
337pub type ByswW<'a, REG> = crate::BitWriter<'a, REG, Bysw>;
338impl<'a, REG> ByswW<'a, REG>
339where
340    REG: crate::Writable + crate::RegisterSpec,
341{
342    #[doc = "Disable byte swap"]
343    #[inline(always)]
344    pub fn disabled(self) -> &'a mut crate::W<REG> {
345        self.variant(Bysw::Disabled)
346    }
347    #[doc = "Enable byte swap"]
348    #[inline(always)]
349    pub fn enabled(self) -> &'a mut crate::W<REG> {
350        self.variant(Bysw::Enabled)
351    }
352}
353#[doc = "LSB First\n\nValue on reset: 0"]
354#[cfg_attr(feature = "defmt", derive(defmt::Format))]
355#[derive(Clone, Copy, Debug, PartialEq, Eq)]
356pub enum Lsbf {
357    #[doc = "0: MSB first"]
358    MsbFirst = 0,
359    #[doc = "1: LSB first"]
360    LsbFirst = 1,
361}
362impl From<Lsbf> for bool {
363    #[inline(always)]
364    fn from(variant: Lsbf) -> Self {
365        variant as u8 != 0
366    }
367}
368#[doc = "Field `LSBF` reader - LSB First"]
369pub type LsbfR = crate::BitReader<Lsbf>;
370impl LsbfR {
371    #[doc = "Get enumerated values variant"]
372    #[inline(always)]
373    pub const fn variant(&self) -> Lsbf {
374        match self.bits {
375            false => Lsbf::MsbFirst,
376            true => Lsbf::LsbFirst,
377        }
378    }
379    #[doc = "MSB first"]
380    #[inline(always)]
381    pub fn is_msb_first(&self) -> bool {
382        *self == Lsbf::MsbFirst
383    }
384    #[doc = "LSB first"]
385    #[inline(always)]
386    pub fn is_lsb_first(&self) -> bool {
387        *self == Lsbf::LsbFirst
388    }
389}
390#[doc = "Field `LSBF` writer - LSB First"]
391pub type LsbfW<'a, REG> = crate::BitWriter<'a, REG, Lsbf>;
392impl<'a, REG> LsbfW<'a, REG>
393where
394    REG: crate::Writable + crate::RegisterSpec,
395{
396    #[doc = "MSB first"]
397    #[inline(always)]
398    pub fn msb_first(self) -> &'a mut crate::W<REG> {
399        self.variant(Lsbf::MsbFirst)
400    }
401    #[doc = "LSB first"]
402    #[inline(always)]
403    pub fn lsb_first(self) -> &'a mut crate::W<REG> {
404        self.variant(Lsbf::LsbFirst)
405    }
406}
407#[doc = "Peripheral Chip Select\n\nValue on reset: 0"]
408#[cfg_attr(feature = "defmt", derive(defmt::Format))]
409#[derive(Clone, Copy, Debug, PartialEq, Eq)]
410#[repr(u8)]
411pub enum Pcs {
412    #[doc = "0: Transfer using PCS\\[0\\]"]
413    TxPcs0 = 0,
414    #[doc = "1: Transfer using PCS\\[1\\]"]
415    TxPcs1 = 1,
416    #[doc = "2: Transfer using PCS\\[2\\]"]
417    TxPcs2 = 2,
418    #[doc = "3: Transfer using PCS\\[3\\]"]
419    TxPcs3 = 3,
420}
421impl From<Pcs> for u8 {
422    #[inline(always)]
423    fn from(variant: Pcs) -> Self {
424        variant as _
425    }
426}
427impl crate::FieldSpec for Pcs {
428    type Ux = u8;
429}
430impl crate::IsEnum for Pcs {}
431#[doc = "Field `PCS` reader - Peripheral Chip Select"]
432pub type PcsR = crate::FieldReader<Pcs>;
433impl PcsR {
434    #[doc = "Get enumerated values variant"]
435    #[inline(always)]
436    pub const fn variant(&self) -> Pcs {
437        match self.bits {
438            0 => Pcs::TxPcs0,
439            1 => Pcs::TxPcs1,
440            2 => Pcs::TxPcs2,
441            3 => Pcs::TxPcs3,
442            _ => unreachable!(),
443        }
444    }
445    #[doc = "Transfer using PCS\\[0\\]"]
446    #[inline(always)]
447    pub fn is_tx_pcs0(&self) -> bool {
448        *self == Pcs::TxPcs0
449    }
450    #[doc = "Transfer using PCS\\[1\\]"]
451    #[inline(always)]
452    pub fn is_tx_pcs1(&self) -> bool {
453        *self == Pcs::TxPcs1
454    }
455    #[doc = "Transfer using PCS\\[2\\]"]
456    #[inline(always)]
457    pub fn is_tx_pcs2(&self) -> bool {
458        *self == Pcs::TxPcs2
459    }
460    #[doc = "Transfer using PCS\\[3\\]"]
461    #[inline(always)]
462    pub fn is_tx_pcs3(&self) -> bool {
463        *self == Pcs::TxPcs3
464    }
465}
466#[doc = "Field `PCS` writer - Peripheral Chip Select"]
467pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pcs, crate::Safe>;
468impl<'a, REG> PcsW<'a, REG>
469where
470    REG: crate::Writable + crate::RegisterSpec,
471    REG::Ux: From<u8>,
472{
473    #[doc = "Transfer using PCS\\[0\\]"]
474    #[inline(always)]
475    pub fn tx_pcs0(self) -> &'a mut crate::W<REG> {
476        self.variant(Pcs::TxPcs0)
477    }
478    #[doc = "Transfer using PCS\\[1\\]"]
479    #[inline(always)]
480    pub fn tx_pcs1(self) -> &'a mut crate::W<REG> {
481        self.variant(Pcs::TxPcs1)
482    }
483    #[doc = "Transfer using PCS\\[2\\]"]
484    #[inline(always)]
485    pub fn tx_pcs2(self) -> &'a mut crate::W<REG> {
486        self.variant(Pcs::TxPcs2)
487    }
488    #[doc = "Transfer using PCS\\[3\\]"]
489    #[inline(always)]
490    pub fn tx_pcs3(self) -> &'a mut crate::W<REG> {
491        self.variant(Pcs::TxPcs3)
492    }
493}
494#[doc = "Prescaler Value\n\nValue on reset: 0"]
495#[cfg_attr(feature = "defmt", derive(defmt::Format))]
496#[derive(Clone, Copy, Debug, PartialEq, Eq)]
497#[repr(u8)]
498pub enum Prescale {
499    #[doc = "0: Divide by 1"]
500    Divideby1 = 0,
501    #[doc = "1: Divide by 2"]
502    Divideby2 = 1,
503    #[doc = "2: Divide by 4"]
504    Divideby4 = 2,
505    #[doc = "3: Divide by 8"]
506    Divideby8 = 3,
507    #[doc = "4: Divide by 16"]
508    Divideby16 = 4,
509    #[doc = "5: Divide by 32"]
510    Divideby32 = 5,
511    #[doc = "6: Divide by 64"]
512    Divideby64 = 6,
513    #[doc = "7: Divide by 128"]
514    Divideby128 = 7,
515}
516impl From<Prescale> for u8 {
517    #[inline(always)]
518    fn from(variant: Prescale) -> Self {
519        variant as _
520    }
521}
522impl crate::FieldSpec for Prescale {
523    type Ux = u8;
524}
525impl crate::IsEnum for Prescale {}
526#[doc = "Field `PRESCALE` reader - Prescaler Value"]
527pub type PrescaleR = crate::FieldReader<Prescale>;
528impl PrescaleR {
529    #[doc = "Get enumerated values variant"]
530    #[inline(always)]
531    pub const fn variant(&self) -> Prescale {
532        match self.bits {
533            0 => Prescale::Divideby1,
534            1 => Prescale::Divideby2,
535            2 => Prescale::Divideby4,
536            3 => Prescale::Divideby8,
537            4 => Prescale::Divideby16,
538            5 => Prescale::Divideby32,
539            6 => Prescale::Divideby64,
540            7 => Prescale::Divideby128,
541            _ => unreachable!(),
542        }
543    }
544    #[doc = "Divide by 1"]
545    #[inline(always)]
546    pub fn is_divideby1(&self) -> bool {
547        *self == Prescale::Divideby1
548    }
549    #[doc = "Divide by 2"]
550    #[inline(always)]
551    pub fn is_divideby2(&self) -> bool {
552        *self == Prescale::Divideby2
553    }
554    #[doc = "Divide by 4"]
555    #[inline(always)]
556    pub fn is_divideby4(&self) -> bool {
557        *self == Prescale::Divideby4
558    }
559    #[doc = "Divide by 8"]
560    #[inline(always)]
561    pub fn is_divideby8(&self) -> bool {
562        *self == Prescale::Divideby8
563    }
564    #[doc = "Divide by 16"]
565    #[inline(always)]
566    pub fn is_divideby16(&self) -> bool {
567        *self == Prescale::Divideby16
568    }
569    #[doc = "Divide by 32"]
570    #[inline(always)]
571    pub fn is_divideby32(&self) -> bool {
572        *self == Prescale::Divideby32
573    }
574    #[doc = "Divide by 64"]
575    #[inline(always)]
576    pub fn is_divideby64(&self) -> bool {
577        *self == Prescale::Divideby64
578    }
579    #[doc = "Divide by 128"]
580    #[inline(always)]
581    pub fn is_divideby128(&self) -> bool {
582        *self == Prescale::Divideby128
583    }
584}
585#[doc = "Field `PRESCALE` writer - Prescaler Value"]
586pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescale, crate::Safe>;
587impl<'a, REG> PrescaleW<'a, REG>
588where
589    REG: crate::Writable + crate::RegisterSpec,
590    REG::Ux: From<u8>,
591{
592    #[doc = "Divide by 1"]
593    #[inline(always)]
594    pub fn divideby1(self) -> &'a mut crate::W<REG> {
595        self.variant(Prescale::Divideby1)
596    }
597    #[doc = "Divide by 2"]
598    #[inline(always)]
599    pub fn divideby2(self) -> &'a mut crate::W<REG> {
600        self.variant(Prescale::Divideby2)
601    }
602    #[doc = "Divide by 4"]
603    #[inline(always)]
604    pub fn divideby4(self) -> &'a mut crate::W<REG> {
605        self.variant(Prescale::Divideby4)
606    }
607    #[doc = "Divide by 8"]
608    #[inline(always)]
609    pub fn divideby8(self) -> &'a mut crate::W<REG> {
610        self.variant(Prescale::Divideby8)
611    }
612    #[doc = "Divide by 16"]
613    #[inline(always)]
614    pub fn divideby16(self) -> &'a mut crate::W<REG> {
615        self.variant(Prescale::Divideby16)
616    }
617    #[doc = "Divide by 32"]
618    #[inline(always)]
619    pub fn divideby32(self) -> &'a mut crate::W<REG> {
620        self.variant(Prescale::Divideby32)
621    }
622    #[doc = "Divide by 64"]
623    #[inline(always)]
624    pub fn divideby64(self) -> &'a mut crate::W<REG> {
625        self.variant(Prescale::Divideby64)
626    }
627    #[doc = "Divide by 128"]
628    #[inline(always)]
629    pub fn divideby128(self) -> &'a mut crate::W<REG> {
630        self.variant(Prescale::Divideby128)
631    }
632}
633#[doc = "Clock Phase\n\nValue on reset: 0"]
634#[cfg_attr(feature = "defmt", derive(defmt::Format))]
635#[derive(Clone, Copy, Debug, PartialEq, Eq)]
636pub enum Cpha {
637    #[doc = "0: Captured"]
638    Captured = 0,
639    #[doc = "1: Changed"]
640    Changed = 1,
641}
642impl From<Cpha> for bool {
643    #[inline(always)]
644    fn from(variant: Cpha) -> Self {
645        variant as u8 != 0
646    }
647}
648#[doc = "Field `CPHA` reader - Clock Phase"]
649pub type CphaR = crate::BitReader<Cpha>;
650impl CphaR {
651    #[doc = "Get enumerated values variant"]
652    #[inline(always)]
653    pub const fn variant(&self) -> Cpha {
654        match self.bits {
655            false => Cpha::Captured,
656            true => Cpha::Changed,
657        }
658    }
659    #[doc = "Captured"]
660    #[inline(always)]
661    pub fn is_captured(&self) -> bool {
662        *self == Cpha::Captured
663    }
664    #[doc = "Changed"]
665    #[inline(always)]
666    pub fn is_changed(&self) -> bool {
667        *self == Cpha::Changed
668    }
669}
670#[doc = "Field `CPHA` writer - Clock Phase"]
671pub type CphaW<'a, REG> = crate::BitWriter<'a, REG, Cpha>;
672impl<'a, REG> CphaW<'a, REG>
673where
674    REG: crate::Writable + crate::RegisterSpec,
675{
676    #[doc = "Captured"]
677    #[inline(always)]
678    pub fn captured(self) -> &'a mut crate::W<REG> {
679        self.variant(Cpha::Captured)
680    }
681    #[doc = "Changed"]
682    #[inline(always)]
683    pub fn changed(self) -> &'a mut crate::W<REG> {
684        self.variant(Cpha::Changed)
685    }
686}
687#[doc = "Clock Polarity\n\nValue on reset: 0"]
688#[cfg_attr(feature = "defmt", derive(defmt::Format))]
689#[derive(Clone, Copy, Debug, PartialEq, Eq)]
690pub enum Cpol {
691    #[doc = "0: Inactive low"]
692    InactiveLow = 0,
693    #[doc = "1: Inactive high"]
694    InactiveHigh = 1,
695}
696impl From<Cpol> for bool {
697    #[inline(always)]
698    fn from(variant: Cpol) -> Self {
699        variant as u8 != 0
700    }
701}
702#[doc = "Field `CPOL` reader - Clock Polarity"]
703pub type CpolR = crate::BitReader<Cpol>;
704impl CpolR {
705    #[doc = "Get enumerated values variant"]
706    #[inline(always)]
707    pub const fn variant(&self) -> Cpol {
708        match self.bits {
709            false => Cpol::InactiveLow,
710            true => Cpol::InactiveHigh,
711        }
712    }
713    #[doc = "Inactive low"]
714    #[inline(always)]
715    pub fn is_inactive_low(&self) -> bool {
716        *self == Cpol::InactiveLow
717    }
718    #[doc = "Inactive high"]
719    #[inline(always)]
720    pub fn is_inactive_high(&self) -> bool {
721        *self == Cpol::InactiveHigh
722    }
723}
724#[doc = "Field `CPOL` writer - Clock Polarity"]
725pub type CpolW<'a, REG> = crate::BitWriter<'a, REG, Cpol>;
726impl<'a, REG> CpolW<'a, REG>
727where
728    REG: crate::Writable + crate::RegisterSpec,
729{
730    #[doc = "Inactive low"]
731    #[inline(always)]
732    pub fn inactive_low(self) -> &'a mut crate::W<REG> {
733        self.variant(Cpol::InactiveLow)
734    }
735    #[doc = "Inactive high"]
736    #[inline(always)]
737    pub fn inactive_high(self) -> &'a mut crate::W<REG> {
738        self.variant(Cpol::InactiveHigh)
739    }
740}
741impl R {
742    #[doc = "Bits 0:11 - Frame Size"]
743    #[inline(always)]
744    pub fn framesz(&self) -> FrameszR {
745        FrameszR::new((self.bits & 0x0fff) as u16)
746    }
747    #[doc = "Bits 16:17 - Transfer Width"]
748    #[inline(always)]
749    pub fn width(&self) -> WidthR {
750        WidthR::new(((self.bits >> 16) & 3) as u8)
751    }
752    #[doc = "Bit 18 - Transmit Data Mask"]
753    #[inline(always)]
754    pub fn txmsk(&self) -> TxmskR {
755        TxmskR::new(((self.bits >> 18) & 1) != 0)
756    }
757    #[doc = "Bit 19 - Receive Data Mask"]
758    #[inline(always)]
759    pub fn rxmsk(&self) -> RxmskR {
760        RxmskR::new(((self.bits >> 19) & 1) != 0)
761    }
762    #[doc = "Bit 20 - Continuing Command"]
763    #[inline(always)]
764    pub fn contc(&self) -> ContcR {
765        ContcR::new(((self.bits >> 20) & 1) != 0)
766    }
767    #[doc = "Bit 21 - Continuous Transfer"]
768    #[inline(always)]
769    pub fn cont(&self) -> ContR {
770        ContR::new(((self.bits >> 21) & 1) != 0)
771    }
772    #[doc = "Bit 22 - Byte Swap"]
773    #[inline(always)]
774    pub fn bysw(&self) -> ByswR {
775        ByswR::new(((self.bits >> 22) & 1) != 0)
776    }
777    #[doc = "Bit 23 - LSB First"]
778    #[inline(always)]
779    pub fn lsbf(&self) -> LsbfR {
780        LsbfR::new(((self.bits >> 23) & 1) != 0)
781    }
782    #[doc = "Bits 24:25 - Peripheral Chip Select"]
783    #[inline(always)]
784    pub fn pcs(&self) -> PcsR {
785        PcsR::new(((self.bits >> 24) & 3) as u8)
786    }
787    #[doc = "Bits 27:29 - Prescaler Value"]
788    #[inline(always)]
789    pub fn prescale(&self) -> PrescaleR {
790        PrescaleR::new(((self.bits >> 27) & 7) as u8)
791    }
792    #[doc = "Bit 30 - Clock Phase"]
793    #[inline(always)]
794    pub fn cpha(&self) -> CphaR {
795        CphaR::new(((self.bits >> 30) & 1) != 0)
796    }
797    #[doc = "Bit 31 - Clock Polarity"]
798    #[inline(always)]
799    pub fn cpol(&self) -> CpolR {
800        CpolR::new(((self.bits >> 31) & 1) != 0)
801    }
802}
803#[cfg(feature = "debug")]
804impl core::fmt::Debug for R {
805    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
806        f.debug_struct("TCR")
807            .field("framesz", &self.framesz())
808            .field("width", &self.width())
809            .field("txmsk", &self.txmsk())
810            .field("rxmsk", &self.rxmsk())
811            .field("contc", &self.contc())
812            .field("cont", &self.cont())
813            .field("bysw", &self.bysw())
814            .field("lsbf", &self.lsbf())
815            .field("pcs", &self.pcs())
816            .field("prescale", &self.prescale())
817            .field("cpha", &self.cpha())
818            .field("cpol", &self.cpol())
819            .finish()
820    }
821}
822impl W {
823    #[doc = "Bits 0:11 - Frame Size"]
824    #[inline(always)]
825    pub fn framesz(&mut self) -> FrameszW<'_, TcrSpec> {
826        FrameszW::new(self, 0)
827    }
828    #[doc = "Bits 16:17 - Transfer Width"]
829    #[inline(always)]
830    pub fn width(&mut self) -> WidthW<'_, TcrSpec> {
831        WidthW::new(self, 16)
832    }
833    #[doc = "Bit 18 - Transmit Data Mask"]
834    #[inline(always)]
835    pub fn txmsk(&mut self) -> TxmskW<'_, TcrSpec> {
836        TxmskW::new(self, 18)
837    }
838    #[doc = "Bit 19 - Receive Data Mask"]
839    #[inline(always)]
840    pub fn rxmsk(&mut self) -> RxmskW<'_, TcrSpec> {
841        RxmskW::new(self, 19)
842    }
843    #[doc = "Bit 20 - Continuing Command"]
844    #[inline(always)]
845    pub fn contc(&mut self) -> ContcW<'_, TcrSpec> {
846        ContcW::new(self, 20)
847    }
848    #[doc = "Bit 21 - Continuous Transfer"]
849    #[inline(always)]
850    pub fn cont(&mut self) -> ContW<'_, TcrSpec> {
851        ContW::new(self, 21)
852    }
853    #[doc = "Bit 22 - Byte Swap"]
854    #[inline(always)]
855    pub fn bysw(&mut self) -> ByswW<'_, TcrSpec> {
856        ByswW::new(self, 22)
857    }
858    #[doc = "Bit 23 - LSB First"]
859    #[inline(always)]
860    pub fn lsbf(&mut self) -> LsbfW<'_, TcrSpec> {
861        LsbfW::new(self, 23)
862    }
863    #[doc = "Bits 24:25 - Peripheral Chip Select"]
864    #[inline(always)]
865    pub fn pcs(&mut self) -> PcsW<'_, TcrSpec> {
866        PcsW::new(self, 24)
867    }
868    #[doc = "Bits 27:29 - Prescaler Value"]
869    #[inline(always)]
870    pub fn prescale(&mut self) -> PrescaleW<'_, TcrSpec> {
871        PrescaleW::new(self, 27)
872    }
873    #[doc = "Bit 30 - Clock Phase"]
874    #[inline(always)]
875    pub fn cpha(&mut self) -> CphaW<'_, TcrSpec> {
876        CphaW::new(self, 30)
877    }
878    #[doc = "Bit 31 - Clock Polarity"]
879    #[inline(always)]
880    pub fn cpol(&mut self) -> CpolW<'_, TcrSpec> {
881        CpolW::new(self, 31)
882    }
883}
884#[doc = "Transmit Command\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
885pub struct TcrSpec;
886impl crate::RegisterSpec for TcrSpec {
887    type Ux = u32;
888}
889#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
890impl crate::Readable for TcrSpec {}
891#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
892impl crate::Writable for TcrSpec {
893    type Safety = crate::Unsafe;
894}
895#[doc = "`reset()` method sets TCR to value 0x1f"]
896impl crate::Resettable for TcrSpec {
897    const RESET_VALUE: u32 = 0x1f;
898}
mcxa_pac/lpspi0/tcr.rs

mcxa_pac/lpspi0/
tcr.rs
