mcxa_pac/lpspi0/
der.rs

1#[doc = "Register `DER` reader"]
2pub type R = crate::R<DerSpec>;
3#[doc = "Register `DER` writer"]
4pub type W = crate::W<DerSpec>;
5#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Tdde {
9    #[doc = "0: Disable"]
10    Disable = 0,
11    #[doc = "1: Enable"]
12    Enable = 1,
13}
14impl From<Tdde> for bool {
15    #[inline(always)]
16    fn from(variant: Tdde) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"]
21pub type TddeR = crate::BitReader<Tdde>;
22impl TddeR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Tdde {
26        match self.bits {
27            false => Tdde::Disable,
28            true => Tdde::Enable,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Tdde::Disable
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Tdde::Enable
40    }
41}
42#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"]
43pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>;
44impl<'a, REG> TddeW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Tdde::Disable)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Tdde::Enable)
57    }
58}
59#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Rdde {
63    #[doc = "0: Disable"]
64    Disable = 0,
65    #[doc = "1: Enable"]
66    Enable = 1,
67}
68impl From<Rdde> for bool {
69    #[inline(always)]
70    fn from(variant: Rdde) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `RDDE` reader - Receive Data DMA Enable"]
75pub type RddeR = crate::BitReader<Rdde>;
76impl RddeR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Rdde {
80        match self.bits {
81            false => Rdde::Disable,
82            true => Rdde::Enable,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Rdde::Disable
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Rdde::Enable
94    }
95}
96#[doc = "Field `RDDE` writer - Receive Data DMA Enable"]
97pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>;
98impl<'a, REG> RddeW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Rdde::Disable)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Rdde::Enable)
111    }
112}
113#[doc = "Frame Complete DMA Enable\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Fcde {
117    #[doc = "0: Disable"]
118    Disable = 0,
119    #[doc = "1: Enable"]
120    Enable = 1,
121}
122impl From<Fcde> for bool {
123    #[inline(always)]
124    fn from(variant: Fcde) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `FCDE` reader - Frame Complete DMA Enable"]
129pub type FcdeR = crate::BitReader<Fcde>;
130impl FcdeR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Fcde {
134        match self.bits {
135            false => Fcde::Disable,
136            true => Fcde::Enable,
137        }
138    }
139    #[doc = "Disable"]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == Fcde::Disable
143    }
144    #[doc = "Enable"]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == Fcde::Enable
148    }
149}
150#[doc = "Field `FCDE` writer - Frame Complete DMA Enable"]
151pub type FcdeW<'a, REG> = crate::BitWriter<'a, REG, Fcde>;
152impl<'a, REG> FcdeW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Disable"]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(Fcde::Disable)
160    }
161    #[doc = "Enable"]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(Fcde::Enable)
165    }
166}
167impl R {
168    #[doc = "Bit 0 - Transmit Data DMA Enable"]
169    #[inline(always)]
170    pub fn tdde(&self) -> TddeR {
171        TddeR::new((self.bits & 1) != 0)
172    }
173    #[doc = "Bit 1 - Receive Data DMA Enable"]
174    #[inline(always)]
175    pub fn rdde(&self) -> RddeR {
176        RddeR::new(((self.bits >> 1) & 1) != 0)
177    }
178    #[doc = "Bit 9 - Frame Complete DMA Enable"]
179    #[inline(always)]
180    pub fn fcde(&self) -> FcdeR {
181        FcdeR::new(((self.bits >> 9) & 1) != 0)
182    }
183}
184#[cfg(feature = "debug")]
185impl core::fmt::Debug for R {
186    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
187        f.debug_struct("DER")
188            .field("tdde", &self.tdde())
189            .field("rdde", &self.rdde())
190            .field("fcde", &self.fcde())
191            .finish()
192    }
193}
194impl W {
195    #[doc = "Bit 0 - Transmit Data DMA Enable"]
196    #[inline(always)]
197    pub fn tdde(&mut self) -> TddeW<'_, DerSpec> {
198        TddeW::new(self, 0)
199    }
200    #[doc = "Bit 1 - Receive Data DMA Enable"]
201    #[inline(always)]
202    pub fn rdde(&mut self) -> RddeW<'_, DerSpec> {
203        RddeW::new(self, 1)
204    }
205    #[doc = "Bit 9 - Frame Complete DMA Enable"]
206    #[inline(always)]
207    pub fn fcde(&mut self) -> FcdeW<'_, DerSpec> {
208        FcdeW::new(self, 9)
209    }
210}
211#[doc = "DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct DerSpec;
213impl crate::RegisterSpec for DerSpec {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`der::R`](R) reader structure"]
217impl crate::Readable for DerSpec {}
218#[doc = "`write(|w| ..)` method takes [`der::W`](W) writer structure"]
219impl crate::Writable for DerSpec {
220    type Safety = crate::Unsafe;
221}
222#[doc = "`reset()` method sets DER to value 0"]
223impl crate::Resettable for DerSpec {}
mcxa_pac/lpspi0/der.rs

mcxa_pac/lpspi0/
der.rs
