mcxa_pac/lpi2c0/
mtdr.rs

1#[doc = "Register `MTDR` writer"]
2pub type W = crate::W<MtdrSpec>;
3#[doc = "Field `DATA` writer - Transmit Data"]
4pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5#[doc = "Command Data\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Cmd {
10    #[doc = "0: Transmit value in DATA\\[7:0\\]"]
11    Transmit = 0,
12    #[doc = "1: Receive (DATA\\[7:0\\] + 1) bytes."]
13    Receive = 1,
14    #[doc = "2: Generate Stop condition on I2C bus."]
15    Stop = 2,
16    #[doc = "3: Receive and discard (DATA\\[7:0\\] + 1) bytes."]
17    ReceiveAndDiscard = 3,
18    #[doc = "4: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\]"]
19    Start = 4,
20    #[doc = "5: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] expecting a NACK response"]
21    StartExpectNack = 5,
22    #[doc = "6: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode"]
23    StartHs = 6,
24    #[doc = "7: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode expecting a NACK response"]
25    StartHsExpectNack = 7,
26}
27impl From<Cmd> for u8 {
28    #[inline(always)]
29    fn from(variant: Cmd) -> Self {
30        variant as _
31    }
32}
33impl crate::FieldSpec for Cmd {
34    type Ux = u8;
35}
36impl crate::IsEnum for Cmd {}
37#[doc = "Field `CMD` writer - Command Data"]
38pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 3, Cmd, crate::Safe>;
39impl<'a, REG> CmdW<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42    REG::Ux: From<u8>,
43{
44    #[doc = "Transmit value in DATA\\[7:0\\]"]
45    #[inline(always)]
46    pub fn transmit(self) -> &'a mut crate::W<REG> {
47        self.variant(Cmd::Transmit)
48    }
49    #[doc = "Receive (DATA\\[7:0\\] + 1) bytes."]
50    #[inline(always)]
51    pub fn receive(self) -> &'a mut crate::W<REG> {
52        self.variant(Cmd::Receive)
53    }
54    #[doc = "Generate Stop condition on I2C bus."]
55    #[inline(always)]
56    pub fn stop(self) -> &'a mut crate::W<REG> {
57        self.variant(Cmd::Stop)
58    }
59    #[doc = "Receive and discard (DATA\\[7:0\\] + 1) bytes."]
60    #[inline(always)]
61    pub fn receive_and_discard(self) -> &'a mut crate::W<REG> {
62        self.variant(Cmd::ReceiveAndDiscard)
63    }
64    #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\]"]
65    #[inline(always)]
66    pub fn start(self) -> &'a mut crate::W<REG> {
67        self.variant(Cmd::Start)
68    }
69    #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] expecting a NACK response"]
70    #[inline(always)]
71    pub fn start_expect_nack(self) -> &'a mut crate::W<REG> {
72        self.variant(Cmd::StartExpectNack)
73    }
74    #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode"]
75    #[inline(always)]
76    pub fn start_hs(self) -> &'a mut crate::W<REG> {
77        self.variant(Cmd::StartHs)
78    }
79    #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode expecting a NACK response"]
80    #[inline(always)]
81    pub fn start_hs_expect_nack(self) -> &'a mut crate::W<REG> {
82        self.variant(Cmd::StartHsExpectNack)
83    }
84}
85#[cfg(feature = "debug")]
86impl core::fmt::Debug for crate::generic::Reg<MtdrSpec> {
87    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
88        write!(f, "(not readable)")
89    }
90}
91impl W {
92    #[doc = "Bits 0:7 - Transmit Data"]
93    #[inline(always)]
94    pub fn data(&mut self) -> DataW<'_, MtdrSpec> {
95        DataW::new(self, 0)
96    }
97    #[doc = "Bits 8:10 - Command Data"]
98    #[inline(always)]
99    pub fn cmd(&mut self) -> CmdW<'_, MtdrSpec> {
100        CmdW::new(self, 8)
101    }
102}
103#[doc = "Controller Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
104pub struct MtdrSpec;
105impl crate::RegisterSpec for MtdrSpec {
106    type Ux = u32;
107}
108#[doc = "`write(|w| ..)` method takes [`mtdr::W`](W) writer structure"]
109impl crate::Writable for MtdrSpec {
110    type Safety = crate::Unsafe;
111}
112#[doc = "`reset()` method sets MTDR to value 0"]
113impl crate::Resettable for MtdrSpec {}
mcxa_pac/lpi2c0/mtdr.rs

mcxa_pac/lpi2c0/
mtdr.rs
