mcxa_pac/lpi2c0/
mder.rs

1#[doc = "Register `MDER` reader"]
2pub type R = crate::R<MderSpec>;
3#[doc = "Register `MDER` writer"]
4pub type W = crate::W<MderSpec>;
5#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Tdde {
9    #[doc = "0: Disable"]
10    Disabled = 0,
11    #[doc = "1: Enable"]
12    Enabled = 1,
13}
14impl From<Tdde> for bool {
15    #[inline(always)]
16    fn from(variant: Tdde) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"]
21pub type TddeR = crate::BitReader<Tdde>;
22impl TddeR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Tdde {
26        match self.bits {
27            false => Tdde::Disabled,
28            true => Tdde::Enabled,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Tdde::Disabled
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Tdde::Enabled
40    }
41}
42#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"]
43pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>;
44impl<'a, REG> TddeW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Tdde::Disabled)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Tdde::Enabled)
57    }
58}
59#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Rdde {
63    #[doc = "0: Disable"]
64    Disabled = 0,
65    #[doc = "1: Enable"]
66    Enabled = 1,
67}
68impl From<Rdde> for bool {
69    #[inline(always)]
70    fn from(variant: Rdde) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `RDDE` reader - Receive Data DMA Enable"]
75pub type RddeR = crate::BitReader<Rdde>;
76impl RddeR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Rdde {
80        match self.bits {
81            false => Rdde::Disabled,
82            true => Rdde::Enabled,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_disabled(&self) -> bool {
88        *self == Rdde::Disabled
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_enabled(&self) -> bool {
93        *self == Rdde::Enabled
94    }
95}
96#[doc = "Field `RDDE` writer - Receive Data DMA Enable"]
97pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>;
98impl<'a, REG> RddeW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn disabled(self) -> &'a mut crate::W<REG> {
105        self.variant(Rdde::Disabled)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn enabled(self) -> &'a mut crate::W<REG> {
110        self.variant(Rdde::Enabled)
111    }
112}
113impl R {
114    #[doc = "Bit 0 - Transmit Data DMA Enable"]
115    #[inline(always)]
116    pub fn tdde(&self) -> TddeR {
117        TddeR::new((self.bits & 1) != 0)
118    }
119    #[doc = "Bit 1 - Receive Data DMA Enable"]
120    #[inline(always)]
121    pub fn rdde(&self) -> RddeR {
122        RddeR::new(((self.bits >> 1) & 1) != 0)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("MDER")
129            .field("tdde", &self.tdde())
130            .field("rdde", &self.rdde())
131            .finish()
132    }
133}
134impl W {
135    #[doc = "Bit 0 - Transmit Data DMA Enable"]
136    #[inline(always)]
137    pub fn tdde(&mut self) -> TddeW<'_, MderSpec> {
138        TddeW::new(self, 0)
139    }
140    #[doc = "Bit 1 - Receive Data DMA Enable"]
141    #[inline(always)]
142    pub fn rdde(&mut self) -> RddeW<'_, MderSpec> {
143        RddeW::new(self, 1)
144    }
145}
146#[doc = "Controller DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mder::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mder::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
147pub struct MderSpec;
148impl crate::RegisterSpec for MderSpec {
149    type Ux = u32;
150}
151#[doc = "`read()` method returns [`mder::R`](R) reader structure"]
152impl crate::Readable for MderSpec {}
153#[doc = "`write(|w| ..)` method takes [`mder::W`](W) writer structure"]
154impl crate::Writable for MderSpec {
155    type Safety = crate::Unsafe;
156}
157#[doc = "`reset()` method sets MDER to value 0"]
158impl crate::Resettable for MderSpec {}
mcxa_pac/lpi2c0/mder.rs

mcxa_pac/lpi2c0/
mder.rs
