mcxa_pac/inputmux0/
pwm0_ext_clk.rs

1#[doc = "Register `PWM0_EXT_CLK` reader"]
2pub type R = crate::R<Pwm0ExtClkSpec>;
3#[doc = "Register `PWM0_EXT_CLK` writer"]
4pub type W = crate::W<Pwm0ExtClkSpec>;
5#[doc = "Trigger input connections for PWM\n\nValue on reset: 15"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Trigin {
10    #[doc = "1: clk_16k\\[1\\] input is selected"]
11    Val1 = 1,
12    #[doc = "2: clk_in input is selected"]
13    Val2 = 2,
14    #[doc = "3: AOI0_OUT0 input is selected"]
15    Val3 = 3,
16    #[doc = "4: AOI0_OUT1 input is selected"]
17    Val4 = 4,
18    #[doc = "5: EXTTRIG_IN0 input is selected"]
19    Val5 = 5,
20    #[doc = "6: EXTTRIG_IN7 input is selected"]
21    Val6 = 6,
22    #[doc = "7: AOI1_OUT0 input is selected"]
23    Val7 = 7,
24    #[doc = "8: AOI1_OUT1 input is selected"]
25    Val8 = 8,
26}
27impl From<Trigin> for u8 {
28    #[inline(always)]
29    fn from(variant: Trigin) -> Self {
30        variant as _
31    }
32}
33impl crate::FieldSpec for Trigin {
34    type Ux = u8;
35}
36impl crate::IsEnum for Trigin {}
37#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM"]
38pub type TriginR = crate::FieldReader<Trigin>;
39impl TriginR {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Option<Trigin> {
43        match self.bits {
44            1 => Some(Trigin::Val1),
45            2 => Some(Trigin::Val2),
46            3 => Some(Trigin::Val3),
47            4 => Some(Trigin::Val4),
48            5 => Some(Trigin::Val5),
49            6 => Some(Trigin::Val6),
50            7 => Some(Trigin::Val7),
51            8 => Some(Trigin::Val8),
52            _ => None,
53        }
54    }
55    #[doc = "clk_16k\\[1\\] input is selected"]
56    #[inline(always)]
57    pub fn is_val1(&self) -> bool {
58        *self == Trigin::Val1
59    }
60    #[doc = "clk_in input is selected"]
61    #[inline(always)]
62    pub fn is_val2(&self) -> bool {
63        *self == Trigin::Val2
64    }
65    #[doc = "AOI0_OUT0 input is selected"]
66    #[inline(always)]
67    pub fn is_val3(&self) -> bool {
68        *self == Trigin::Val3
69    }
70    #[doc = "AOI0_OUT1 input is selected"]
71    #[inline(always)]
72    pub fn is_val4(&self) -> bool {
73        *self == Trigin::Val4
74    }
75    #[doc = "EXTTRIG_IN0 input is selected"]
76    #[inline(always)]
77    pub fn is_val5(&self) -> bool {
78        *self == Trigin::Val5
79    }
80    #[doc = "EXTTRIG_IN7 input is selected"]
81    #[inline(always)]
82    pub fn is_val6(&self) -> bool {
83        *self == Trigin::Val6
84    }
85    #[doc = "AOI1_OUT0 input is selected"]
86    #[inline(always)]
87    pub fn is_val7(&self) -> bool {
88        *self == Trigin::Val7
89    }
90    #[doc = "AOI1_OUT1 input is selected"]
91    #[inline(always)]
92    pub fn is_val8(&self) -> bool {
93        *self == Trigin::Val8
94    }
95}
96#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM"]
97pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 4, Trigin>;
98impl<'a, REG> TriginW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101    REG::Ux: From<u8>,
102{
103    #[doc = "clk_16k\\[1\\] input is selected"]
104    #[inline(always)]
105    pub fn val1(self) -> &'a mut crate::W<REG> {
106        self.variant(Trigin::Val1)
107    }
108    #[doc = "clk_in input is selected"]
109    #[inline(always)]
110    pub fn val2(self) -> &'a mut crate::W<REG> {
111        self.variant(Trigin::Val2)
112    }
113    #[doc = "AOI0_OUT0 input is selected"]
114    #[inline(always)]
115    pub fn val3(self) -> &'a mut crate::W<REG> {
116        self.variant(Trigin::Val3)
117    }
118    #[doc = "AOI0_OUT1 input is selected"]
119    #[inline(always)]
120    pub fn val4(self) -> &'a mut crate::W<REG> {
121        self.variant(Trigin::Val4)
122    }
123    #[doc = "EXTTRIG_IN0 input is selected"]
124    #[inline(always)]
125    pub fn val5(self) -> &'a mut crate::W<REG> {
126        self.variant(Trigin::Val5)
127    }
128    #[doc = "EXTTRIG_IN7 input is selected"]
129    #[inline(always)]
130    pub fn val6(self) -> &'a mut crate::W<REG> {
131        self.variant(Trigin::Val6)
132    }
133    #[doc = "AOI1_OUT0 input is selected"]
134    #[inline(always)]
135    pub fn val7(self) -> &'a mut crate::W<REG> {
136        self.variant(Trigin::Val7)
137    }
138    #[doc = "AOI1_OUT1 input is selected"]
139    #[inline(always)]
140    pub fn val8(self) -> &'a mut crate::W<REG> {
141        self.variant(Trigin::Val8)
142    }
143}
144impl R {
145    #[doc = "Bits 0:3 - Trigger input connections for PWM"]
146    #[inline(always)]
147    pub fn trigin(&self) -> TriginR {
148        TriginR::new((self.bits & 0x0f) as u8)
149    }
150}
151#[cfg(feature = "debug")]
152impl core::fmt::Debug for R {
153    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
154        f.debug_struct("PWM0_EXT_CLK").field("trigin", &self.trigin()).finish()
155    }
156}
157impl W {
158    #[doc = "Bits 0:3 - Trigger input connections for PWM"]
159    #[inline(always)]
160    pub fn trigin(&mut self) -> TriginW<'_, Pwm0ExtClkSpec> {
161        TriginW::new(self, 0)
162    }
163}
164#[doc = "PWM0 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0_ext_clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0_ext_clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
165pub struct Pwm0ExtClkSpec;
166impl crate::RegisterSpec for Pwm0ExtClkSpec {
167    type Ux = u32;
168}
169#[doc = "`read()` method returns [`pwm0_ext_clk::R`](R) reader structure"]
170impl crate::Readable for Pwm0ExtClkSpec {}
171#[doc = "`write(|w| ..)` method takes [`pwm0_ext_clk::W`](W) writer structure"]
172impl crate::Writable for Pwm0ExtClkSpec {
173    type Safety = crate::Unsafe;
174}
175#[doc = "`reset()` method sets PWM0_EXT_CLK to value 0x0f"]
176impl crate::Resettable for Pwm0ExtClkSpec {
177    const RESET_VALUE: u32 = 0x0f;
178}
mcxa_pac/inputmux0/pwm0_ext_clk.rs

mcxa_pac/inputmux0/
pwm0_ext_clk.rs
