mcxa_pac/inputmux0/
ext_trig.rs

1#[doc = "Register `EXT_TRIG[%s]` reader"]
2pub type R = crate::R<ExtTrigSpec>;
3#[doc = "Register `EXT_TRIG[%s]` writer"]
4pub type W = crate::W<ExtTrigSpec>;
5#[doc = "EXT trigger input connections\n\nValue on reset: 31"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Inp {
10    #[doc = "2: AOI0_OUT0 input is selected"]
11    Val2 = 2,
12    #[doc = "3: AOI0_OUT1 input is selected"]
13    Val3 = 3,
14    #[doc = "4: AOI0_OUT2 input is selected"]
15    Val4 = 4,
16    #[doc = "5: AOI0_OUT3 input is selected"]
17    Val5 = 5,
18    #[doc = "6: CMP0_OUT input is selected"]
19    Val6 = 6,
20    #[doc = "7: CMP1_OUT input is selected"]
21    Val7 = 7,
22    #[doc = "8: CMP2_OUT input is selected"]
23    Val8 = 8,
24    #[doc = "9: LPUART0 ipp_do_lpuart_txd input is selected"]
25    Val9 = 9,
26    #[doc = "10: LPUART1 ipp_do_lpuart_txd input is selected"]
27    Val10 = 10,
28    #[doc = "11: LPUART2 ipp_do_lpuart_txd input is selected"]
29    Val11 = 11,
30    #[doc = "12: LPUART3 ipp_do_lpuart_txd input is selected"]
31    Val12 = 12,
32    #[doc = "13: LPUART4 ipp_do_lpuart_txd input is selected"]
33    Val13 = 13,
34    #[doc = "14: AOI1_OUT0 input is selected"]
35    Val14 = 14,
36    #[doc = "15: AOI1_OUT1 input is selected"]
37    Val15 = 15,
38    #[doc = "16: AOI1_OUT2 input is selected"]
39    Val16 = 16,
40    #[doc = "17: RTC_1Hz_CLK input is selected"]
41    Val17 = 17,
42    #[doc = "18: LPUART5 ipp_do_lpuart_txd input is selected"]
43    Val18 = 18,
44}
45impl From<Inp> for u8 {
46    #[inline(always)]
47    fn from(variant: Inp) -> Self {
48        variant as _
49    }
50}
51impl crate::FieldSpec for Inp {
52    type Ux = u8;
53}
54impl crate::IsEnum for Inp {}
55#[doc = "Field `INP` reader - EXT trigger input connections"]
56pub type InpR = crate::FieldReader<Inp>;
57impl InpR {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub const fn variant(&self) -> Option<Inp> {
61        match self.bits {
62            2 => Some(Inp::Val2),
63            3 => Some(Inp::Val3),
64            4 => Some(Inp::Val4),
65            5 => Some(Inp::Val5),
66            6 => Some(Inp::Val6),
67            7 => Some(Inp::Val7),
68            8 => Some(Inp::Val8),
69            9 => Some(Inp::Val9),
70            10 => Some(Inp::Val10),
71            11 => Some(Inp::Val11),
72            12 => Some(Inp::Val12),
73            13 => Some(Inp::Val13),
74            14 => Some(Inp::Val14),
75            15 => Some(Inp::Val15),
76            16 => Some(Inp::Val16),
77            17 => Some(Inp::Val17),
78            18 => Some(Inp::Val18),
79            _ => None,
80        }
81    }
82    #[doc = "AOI0_OUT0 input is selected"]
83    #[inline(always)]
84    pub fn is_val2(&self) -> bool {
85        *self == Inp::Val2
86    }
87    #[doc = "AOI0_OUT1 input is selected"]
88    #[inline(always)]
89    pub fn is_val3(&self) -> bool {
90        *self == Inp::Val3
91    }
92    #[doc = "AOI0_OUT2 input is selected"]
93    #[inline(always)]
94    pub fn is_val4(&self) -> bool {
95        *self == Inp::Val4
96    }
97    #[doc = "AOI0_OUT3 input is selected"]
98    #[inline(always)]
99    pub fn is_val5(&self) -> bool {
100        *self == Inp::Val5
101    }
102    #[doc = "CMP0_OUT input is selected"]
103    #[inline(always)]
104    pub fn is_val6(&self) -> bool {
105        *self == Inp::Val6
106    }
107    #[doc = "CMP1_OUT input is selected"]
108    #[inline(always)]
109    pub fn is_val7(&self) -> bool {
110        *self == Inp::Val7
111    }
112    #[doc = "CMP2_OUT input is selected"]
113    #[inline(always)]
114    pub fn is_val8(&self) -> bool {
115        *self == Inp::Val8
116    }
117    #[doc = "LPUART0 ipp_do_lpuart_txd input is selected"]
118    #[inline(always)]
119    pub fn is_val9(&self) -> bool {
120        *self == Inp::Val9
121    }
122    #[doc = "LPUART1 ipp_do_lpuart_txd input is selected"]
123    #[inline(always)]
124    pub fn is_val10(&self) -> bool {
125        *self == Inp::Val10
126    }
127    #[doc = "LPUART2 ipp_do_lpuart_txd input is selected"]
128    #[inline(always)]
129    pub fn is_val11(&self) -> bool {
130        *self == Inp::Val11
131    }
132    #[doc = "LPUART3 ipp_do_lpuart_txd input is selected"]
133    #[inline(always)]
134    pub fn is_val12(&self) -> bool {
135        *self == Inp::Val12
136    }
137    #[doc = "LPUART4 ipp_do_lpuart_txd input is selected"]
138    #[inline(always)]
139    pub fn is_val13(&self) -> bool {
140        *self == Inp::Val13
141    }
142    #[doc = "AOI1_OUT0 input is selected"]
143    #[inline(always)]
144    pub fn is_val14(&self) -> bool {
145        *self == Inp::Val14
146    }
147    #[doc = "AOI1_OUT1 input is selected"]
148    #[inline(always)]
149    pub fn is_val15(&self) -> bool {
150        *self == Inp::Val15
151    }
152    #[doc = "AOI1_OUT2 input is selected"]
153    #[inline(always)]
154    pub fn is_val16(&self) -> bool {
155        *self == Inp::Val16
156    }
157    #[doc = "RTC_1Hz_CLK input is selected"]
158    #[inline(always)]
159    pub fn is_val17(&self) -> bool {
160        *self == Inp::Val17
161    }
162    #[doc = "LPUART5 ipp_do_lpuart_txd input is selected"]
163    #[inline(always)]
164    pub fn is_val18(&self) -> bool {
165        *self == Inp::Val18
166    }
167}
168#[doc = "Field `INP` writer - EXT trigger input connections"]
169pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 5, Inp>;
170impl<'a, REG> InpW<'a, REG>
171where
172    REG: crate::Writable + crate::RegisterSpec,
173    REG::Ux: From<u8>,
174{
175    #[doc = "AOI0_OUT0 input is selected"]
176    #[inline(always)]
177    pub fn val2(self) -> &'a mut crate::W<REG> {
178        self.variant(Inp::Val2)
179    }
180    #[doc = "AOI0_OUT1 input is selected"]
181    #[inline(always)]
182    pub fn val3(self) -> &'a mut crate::W<REG> {
183        self.variant(Inp::Val3)
184    }
185    #[doc = "AOI0_OUT2 input is selected"]
186    #[inline(always)]
187    pub fn val4(self) -> &'a mut crate::W<REG> {
188        self.variant(Inp::Val4)
189    }
190    #[doc = "AOI0_OUT3 input is selected"]
191    #[inline(always)]
192    pub fn val5(self) -> &'a mut crate::W<REG> {
193        self.variant(Inp::Val5)
194    }
195    #[doc = "CMP0_OUT input is selected"]
196    #[inline(always)]
197    pub fn val6(self) -> &'a mut crate::W<REG> {
198        self.variant(Inp::Val6)
199    }
200    #[doc = "CMP1_OUT input is selected"]
201    #[inline(always)]
202    pub fn val7(self) -> &'a mut crate::W<REG> {
203        self.variant(Inp::Val7)
204    }
205    #[doc = "CMP2_OUT input is selected"]
206    #[inline(always)]
207    pub fn val8(self) -> &'a mut crate::W<REG> {
208        self.variant(Inp::Val8)
209    }
210    #[doc = "LPUART0 ipp_do_lpuart_txd input is selected"]
211    #[inline(always)]
212    pub fn val9(self) -> &'a mut crate::W<REG> {
213        self.variant(Inp::Val9)
214    }
215    #[doc = "LPUART1 ipp_do_lpuart_txd input is selected"]
216    #[inline(always)]
217    pub fn val10(self) -> &'a mut crate::W<REG> {
218        self.variant(Inp::Val10)
219    }
220    #[doc = "LPUART2 ipp_do_lpuart_txd input is selected"]
221    #[inline(always)]
222    pub fn val11(self) -> &'a mut crate::W<REG> {
223        self.variant(Inp::Val11)
224    }
225    #[doc = "LPUART3 ipp_do_lpuart_txd input is selected"]
226    #[inline(always)]
227    pub fn val12(self) -> &'a mut crate::W<REG> {
228        self.variant(Inp::Val12)
229    }
230    #[doc = "LPUART4 ipp_do_lpuart_txd input is selected"]
231    #[inline(always)]
232    pub fn val13(self) -> &'a mut crate::W<REG> {
233        self.variant(Inp::Val13)
234    }
235    #[doc = "AOI1_OUT0 input is selected"]
236    #[inline(always)]
237    pub fn val14(self) -> &'a mut crate::W<REG> {
238        self.variant(Inp::Val14)
239    }
240    #[doc = "AOI1_OUT1 input is selected"]
241    #[inline(always)]
242    pub fn val15(self) -> &'a mut crate::W<REG> {
243        self.variant(Inp::Val15)
244    }
245    #[doc = "AOI1_OUT2 input is selected"]
246    #[inline(always)]
247    pub fn val16(self) -> &'a mut crate::W<REG> {
248        self.variant(Inp::Val16)
249    }
250    #[doc = "RTC_1Hz_CLK input is selected"]
251    #[inline(always)]
252    pub fn val17(self) -> &'a mut crate::W<REG> {
253        self.variant(Inp::Val17)
254    }
255    #[doc = "LPUART5 ipp_do_lpuart_txd input is selected"]
256    #[inline(always)]
257    pub fn val18(self) -> &'a mut crate::W<REG> {
258        self.variant(Inp::Val18)
259    }
260}
261impl R {
262    #[doc = "Bits 0:4 - EXT trigger input connections"]
263    #[inline(always)]
264    pub fn inp(&self) -> InpR {
265        InpR::new((self.bits & 0x1f) as u8)
266    }
267}
268#[cfg(feature = "debug")]
269impl core::fmt::Debug for R {
270    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
271        f.debug_struct("EXT_TRIG").field("inp", &self.inp()).finish()
272    }
273}
274impl W {
275    #[doc = "Bits 0:4 - EXT trigger input connections"]
276    #[inline(always)]
277    pub fn inp(&mut self) -> InpW<'_, ExtTrigSpec> {
278        InpW::new(self, 0)
279    }
280}
281#[doc = "EXT trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
282pub struct ExtTrigSpec;
283impl crate::RegisterSpec for ExtTrigSpec {
284    type Ux = u32;
285}
286#[doc = "`read()` method returns [`ext_trig::R`](R) reader structure"]
287impl crate::Readable for ExtTrigSpec {}
288#[doc = "`write(|w| ..)` method takes [`ext_trig::W`](W) writer structure"]
289impl crate::Writable for ExtTrigSpec {
290    type Safety = crate::Unsafe;
291}
292#[doc = "`reset()` method sets EXT_TRIG[%s] to value 0x1f"]
293impl crate::Resettable for ExtTrigSpec {
294    const RESET_VALUE: u32 = 0x1f;
295}
mcxa_pac/inputmux0/ext_trig.rs

mcxa_pac/inputmux0/
ext_trig.rs
