1#[doc = "Register `SINTCLR` reader"]
2pub type R = crate::R<SintclrSpec>;
3#[doc = "Register `SINTCLR` writer"]
4pub type W = crate::W<SintclrSpec>;
5#[doc = "Field `START` reader - START Interrupt Enable Clear Flag"]
6pub type StartR = crate::BitReader;
7#[doc = "Field `START` writer - START Interrupt Enable Clear Flag"]
8pub type StartW<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `MATCHED` reader - Matched Interrupt Enable Clear Flag"]
10pub type MatchedR = crate::BitReader;
11#[doc = "Field `MATCHED` writer - Matched Interrupt Enable Clear Flag"]
12pub type MatchedW<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `STOP` reader - STOP Interrupt Enable Clear Flag"]
14pub type StopR = crate::BitReader;
15#[doc = "Field `STOP` writer - STOP Interrupt Enable Clear Flag"]
16pub type StopW<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `RXPEND` reader - RXPEND Interrupt Enable Clear Flag"]
18pub type RxpendR = crate::BitReader;
19#[doc = "Field `RXPEND` writer - RXPEND Interrupt Enable Clear Flag"]
20pub type RxpendW<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `TXSEND` reader - TXSEND Interrupt Enable Clear Flag"]
22pub type TxsendR = crate::BitReader;
23#[doc = "Field `TXSEND` writer - TXSEND Interrupt Enable Clear Flag"]
24pub type TxsendW<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `DACHG` reader - DACHG Interrupt Enable Clear Flag"]
26pub type DachgR = crate::BitReader;
27#[doc = "Field `DACHG` writer - DACHG Interrupt Enable Clear Flag"]
28pub type DachgW<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `CCC` reader - CCC Interrupt Enable Clear Flag"]
30pub type CccR = crate::BitReader;
31#[doc = "Field `CCC` writer - CCC Interrupt Enable Clear Flag"]
32pub type CccW<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Enable Clear Flag"]
34pub type ErrwarnR = crate::BitReader;
35#[doc = "Field `ERRWARN` writer - ERRWARN Interrupt Enable Clear Flag"]
36pub type ErrwarnW<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `DDRMATCHED` reader - DDRMATCHED Interrupt Enable Clear Flag"]
38pub type DdrmatchedR = crate::BitReader;
39#[doc = "Field `DDRMATCHED` writer - DDRMATCHED Interrupt Enable Clear Flag"]
40pub type DdrmatchedW<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `CHANDLED` reader - CHANDLED Interrupt Enable Clear Flag"]
42pub type ChandledR = crate::BitReader;
43#[doc = "Field `CHANDLED` writer - CHANDLED Interrupt Enable Clear Flag"]
44pub type ChandledW<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[doc = "Field `EVENT` reader - EVENT Interrupt Enable Clear Flag"]
46pub type EventR = crate::BitReader;
47#[doc = "Field `EVENT` writer - EVENT Interrupt Enable Clear Flag"]
48pub type EventW<'a, REG> = crate::BitWriter1C<'a, REG>;
49impl R {
50 #[doc = "Bit 8 - START Interrupt Enable Clear Flag"]
51 #[inline(always)]
52 pub fn start(&self) -> StartR {
53 StartR::new(((self.bits >> 8) & 1) != 0)
54 }
55 #[doc = "Bit 9 - Matched Interrupt Enable Clear Flag"]
56 #[inline(always)]
57 pub fn matched(&self) -> MatchedR {
58 MatchedR::new(((self.bits >> 9) & 1) != 0)
59 }
60 #[doc = "Bit 10 - STOP Interrupt Enable Clear Flag"]
61 #[inline(always)]
62 pub fn stop(&self) -> StopR {
63 StopR::new(((self.bits >> 10) & 1) != 0)
64 }
65 #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"]
66 #[inline(always)]
67 pub fn rxpend(&self) -> RxpendR {
68 RxpendR::new(((self.bits >> 11) & 1) != 0)
69 }
70 #[doc = "Bit 12 - TXSEND Interrupt Enable Clear Flag"]
71 #[inline(always)]
72 pub fn txsend(&self) -> TxsendR {
73 TxsendR::new(((self.bits >> 12) & 1) != 0)
74 }
75 #[doc = "Bit 13 - DACHG Interrupt Enable Clear Flag"]
76 #[inline(always)]
77 pub fn dachg(&self) -> DachgR {
78 DachgR::new(((self.bits >> 13) & 1) != 0)
79 }
80 #[doc = "Bit 14 - CCC Interrupt Enable Clear Flag"]
81 #[inline(always)]
82 pub fn ccc(&self) -> CccR {
83 CccR::new(((self.bits >> 14) & 1) != 0)
84 }
85 #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"]
86 #[inline(always)]
87 pub fn errwarn(&self) -> ErrwarnR {
88 ErrwarnR::new(((self.bits >> 15) & 1) != 0)
89 }
90 #[doc = "Bit 16 - DDRMATCHED Interrupt Enable Clear Flag"]
91 #[inline(always)]
92 pub fn ddrmatched(&self) -> DdrmatchedR {
93 DdrmatchedR::new(((self.bits >> 16) & 1) != 0)
94 }
95 #[doc = "Bit 17 - CHANDLED Interrupt Enable Clear Flag"]
96 #[inline(always)]
97 pub fn chandled(&self) -> ChandledR {
98 ChandledR::new(((self.bits >> 17) & 1) != 0)
99 }
100 #[doc = "Bit 18 - EVENT Interrupt Enable Clear Flag"]
101 #[inline(always)]
102 pub fn event(&self) -> EventR {
103 EventR::new(((self.bits >> 18) & 1) != 0)
104 }
105}
106#[cfg(feature = "debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("SINTCLR")
110 .field("start", &self.start())
111 .field("matched", &self.matched())
112 .field("stop", &self.stop())
113 .field("rxpend", &self.rxpend())
114 .field("txsend", &self.txsend())
115 .field("dachg", &self.dachg())
116 .field("ccc", &self.ccc())
117 .field("errwarn", &self.errwarn())
118 .field("ddrmatched", &self.ddrmatched())
119 .field("chandled", &self.chandled())
120 .field("event", &self.event())
121 .finish()
122 }
123}
124impl W {
125 #[doc = "Bit 8 - START Interrupt Enable Clear Flag"]
126 #[inline(always)]
127 pub fn start(&mut self) -> StartW<'_, SintclrSpec> {
128 StartW::new(self, 8)
129 }
130 #[doc = "Bit 9 - Matched Interrupt Enable Clear Flag"]
131 #[inline(always)]
132 pub fn matched(&mut self) -> MatchedW<'_, SintclrSpec> {
133 MatchedW::new(self, 9)
134 }
135 #[doc = "Bit 10 - STOP Interrupt Enable Clear Flag"]
136 #[inline(always)]
137 pub fn stop(&mut self) -> StopW<'_, SintclrSpec> {
138 StopW::new(self, 10)
139 }
140 #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"]
141 #[inline(always)]
142 pub fn rxpend(&mut self) -> RxpendW<'_, SintclrSpec> {
143 RxpendW::new(self, 11)
144 }
145 #[doc = "Bit 12 - TXSEND Interrupt Enable Clear Flag"]
146 #[inline(always)]
147 pub fn txsend(&mut self) -> TxsendW<'_, SintclrSpec> {
148 TxsendW::new(self, 12)
149 }
150 #[doc = "Bit 13 - DACHG Interrupt Enable Clear Flag"]
151 #[inline(always)]
152 pub fn dachg(&mut self) -> DachgW<'_, SintclrSpec> {
153 DachgW::new(self, 13)
154 }
155 #[doc = "Bit 14 - CCC Interrupt Enable Clear Flag"]
156 #[inline(always)]
157 pub fn ccc(&mut self) -> CccW<'_, SintclrSpec> {
158 CccW::new(self, 14)
159 }
160 #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"]
161 #[inline(always)]
162 pub fn errwarn(&mut self) -> ErrwarnW<'_, SintclrSpec> {
163 ErrwarnW::new(self, 15)
164 }
165 #[doc = "Bit 16 - DDRMATCHED Interrupt Enable Clear Flag"]
166 #[inline(always)]
167 pub fn ddrmatched(&mut self) -> DdrmatchedW<'_, SintclrSpec> {
168 DdrmatchedW::new(self, 16)
169 }
170 #[doc = "Bit 17 - CHANDLED Interrupt Enable Clear Flag"]
171 #[inline(always)]
172 pub fn chandled(&mut self) -> ChandledW<'_, SintclrSpec> {
173 ChandledW::new(self, 17)
174 }
175 #[doc = "Bit 18 - EVENT Interrupt Enable Clear Flag"]
176 #[inline(always)]
177 pub fn event(&mut self) -> EventW<'_, SintclrSpec> {
178 EventW::new(self, 18)
179 }
180}
181#[doc = "Target Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sintclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct SintclrSpec;
183impl crate::RegisterSpec for SintclrSpec {
184 type Ux = u32;
185}
186#[doc = "`read()` method returns [`sintclr::R`](R) reader structure"]
187impl crate::Readable for SintclrSpec {}
188#[doc = "`write(|w| ..)` method takes [`sintclr::W`](W) writer structure"]
189impl crate::Writable for SintclrSpec {
190 type Safety = crate::Unsafe;
191 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ff00;
192}
193#[doc = "`reset()` method sets SINTCLR to value 0"]
194impl crate::Resettable for SintclrSpec {}