mcxa_pac/i3c0/
mctrl.rs

1#[doc = "Register `MCTRL` reader"]
2pub type R = crate::R<MctrlSpec>;
3#[doc = "Register `MCTRL` writer"]
4pub type W = crate::W<MctrlSpec>;
5#[doc = "Request\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Request {
10    #[doc = "0: NONE"]
11    None = 0,
12    #[doc = "1: EMITSTARTADDR"]
13    Emitstartaddr = 1,
14    #[doc = "2: EMITSTOP"]
15    Emitstop = 2,
16    #[doc = "3: IBIACKNACK"]
17    Ibiacknack = 3,
18    #[doc = "4: PROCESSDAA"]
19    Processdaa = 4,
20    #[doc = "6: Force Exit and Target Reset"]
21    Forceexit = 6,
22    #[doc = "7: AUTOIBI"]
23    Autoibi = 7,
24}
25impl From<Request> for u8 {
26    #[inline(always)]
27    fn from(variant: Request) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for Request {
32    type Ux = u8;
33}
34impl crate::IsEnum for Request {}
35#[doc = "Field `REQUEST` reader - Request"]
36pub type RequestR = crate::FieldReader<Request>;
37impl RequestR {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<Request> {
41        match self.bits {
42            0 => Some(Request::None),
43            1 => Some(Request::Emitstartaddr),
44            2 => Some(Request::Emitstop),
45            3 => Some(Request::Ibiacknack),
46            4 => Some(Request::Processdaa),
47            6 => Some(Request::Forceexit),
48            7 => Some(Request::Autoibi),
49            _ => None,
50        }
51    }
52    #[doc = "NONE"]
53    #[inline(always)]
54    pub fn is_none(&self) -> bool {
55        *self == Request::None
56    }
57    #[doc = "EMITSTARTADDR"]
58    #[inline(always)]
59    pub fn is_emitstartaddr(&self) -> bool {
60        *self == Request::Emitstartaddr
61    }
62    #[doc = "EMITSTOP"]
63    #[inline(always)]
64    pub fn is_emitstop(&self) -> bool {
65        *self == Request::Emitstop
66    }
67    #[doc = "IBIACKNACK"]
68    #[inline(always)]
69    pub fn is_ibiacknack(&self) -> bool {
70        *self == Request::Ibiacknack
71    }
72    #[doc = "PROCESSDAA"]
73    #[inline(always)]
74    pub fn is_processdaa(&self) -> bool {
75        *self == Request::Processdaa
76    }
77    #[doc = "Force Exit and Target Reset"]
78    #[inline(always)]
79    pub fn is_forceexit(&self) -> bool {
80        *self == Request::Forceexit
81    }
82    #[doc = "AUTOIBI"]
83    #[inline(always)]
84    pub fn is_autoibi(&self) -> bool {
85        *self == Request::Autoibi
86    }
87}
88#[doc = "Field `REQUEST` writer - Request"]
89pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 3, Request>;
90impl<'a, REG> RequestW<'a, REG>
91where
92    REG: crate::Writable + crate::RegisterSpec,
93    REG::Ux: From<u8>,
94{
95    #[doc = "NONE"]
96    #[inline(always)]
97    pub fn none(self) -> &'a mut crate::W<REG> {
98        self.variant(Request::None)
99    }
100    #[doc = "EMITSTARTADDR"]
101    #[inline(always)]
102    pub fn emitstartaddr(self) -> &'a mut crate::W<REG> {
103        self.variant(Request::Emitstartaddr)
104    }
105    #[doc = "EMITSTOP"]
106    #[inline(always)]
107    pub fn emitstop(self) -> &'a mut crate::W<REG> {
108        self.variant(Request::Emitstop)
109    }
110    #[doc = "IBIACKNACK"]
111    #[inline(always)]
112    pub fn ibiacknack(self) -> &'a mut crate::W<REG> {
113        self.variant(Request::Ibiacknack)
114    }
115    #[doc = "PROCESSDAA"]
116    #[inline(always)]
117    pub fn processdaa(self) -> &'a mut crate::W<REG> {
118        self.variant(Request::Processdaa)
119    }
120    #[doc = "Force Exit and Target Reset"]
121    #[inline(always)]
122    pub fn forceexit(self) -> &'a mut crate::W<REG> {
123        self.variant(Request::Forceexit)
124    }
125    #[doc = "AUTOIBI"]
126    #[inline(always)]
127    pub fn autoibi(self) -> &'a mut crate::W<REG> {
128        self.variant(Request::Autoibi)
129    }
130}
131#[doc = "Bus Type with EmitStartAddr\n\nValue on reset: 0"]
132#[cfg_attr(feature = "defmt", derive(defmt::Format))]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134#[repr(u8)]
135pub enum Type {
136    #[doc = "0: I3C"]
137    I3c = 0,
138    #[doc = "1: I2C"]
139    I2c = 1,
140    #[doc = "2: DDR"]
141    Ddr = 2,
142}
143impl From<Type> for u8 {
144    #[inline(always)]
145    fn from(variant: Type) -> Self {
146        variant as _
147    }
148}
149impl crate::FieldSpec for Type {
150    type Ux = u8;
151}
152impl crate::IsEnum for Type {}
153#[doc = "Field `TYPE` reader - Bus Type with EmitStartAddr"]
154pub type TypeR = crate::FieldReader<Type>;
155impl TypeR {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub const fn variant(&self) -> Option<Type> {
159        match self.bits {
160            0 => Some(Type::I3c),
161            1 => Some(Type::I2c),
162            2 => Some(Type::Ddr),
163            _ => None,
164        }
165    }
166    #[doc = "I3C"]
167    #[inline(always)]
168    pub fn is_i3c(&self) -> bool {
169        *self == Type::I3c
170    }
171    #[doc = "I2C"]
172    #[inline(always)]
173    pub fn is_i2c(&self) -> bool {
174        *self == Type::I2c
175    }
176    #[doc = "DDR"]
177    #[inline(always)]
178    pub fn is_ddr(&self) -> bool {
179        *self == Type::Ddr
180    }
181}
182#[doc = "Field `TYPE` writer - Bus Type with EmitStartAddr"]
183pub type TypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Type>;
184impl<'a, REG> TypeW<'a, REG>
185where
186    REG: crate::Writable + crate::RegisterSpec,
187    REG::Ux: From<u8>,
188{
189    #[doc = "I3C"]
190    #[inline(always)]
191    pub fn i3c(self) -> &'a mut crate::W<REG> {
192        self.variant(Type::I3c)
193    }
194    #[doc = "I2C"]
195    #[inline(always)]
196    pub fn i2c(self) -> &'a mut crate::W<REG> {
197        self.variant(Type::I2c)
198    }
199    #[doc = "DDR"]
200    #[inline(always)]
201    pub fn ddr(self) -> &'a mut crate::W<REG> {
202        self.variant(Type::Ddr)
203    }
204}
205#[doc = "In-Band Interrupt Response\n\nValue on reset: 0"]
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208#[repr(u8)]
209pub enum Ibiresp {
210    #[doc = "0: ACK (acknowledge)"]
211    Ack = 0,
212    #[doc = "1: NACK (reject)"]
213    Nack = 1,
214    #[doc = "2: Acknowledge with mandatory byte"]
215    AckWithMandatory = 2,
216    #[doc = "3: Manual"]
217    Manual = 3,
218}
219impl From<Ibiresp> for u8 {
220    #[inline(always)]
221    fn from(variant: Ibiresp) -> Self {
222        variant as _
223    }
224}
225impl crate::FieldSpec for Ibiresp {
226    type Ux = u8;
227}
228impl crate::IsEnum for Ibiresp {}
229#[doc = "Field `IBIRESP` reader - In-Band Interrupt Response"]
230pub type IbirespR = crate::FieldReader<Ibiresp>;
231impl IbirespR {
232    #[doc = "Get enumerated values variant"]
233    #[inline(always)]
234    pub const fn variant(&self) -> Ibiresp {
235        match self.bits {
236            0 => Ibiresp::Ack,
237            1 => Ibiresp::Nack,
238            2 => Ibiresp::AckWithMandatory,
239            3 => Ibiresp::Manual,
240            _ => unreachable!(),
241        }
242    }
243    #[doc = "ACK (acknowledge)"]
244    #[inline(always)]
245    pub fn is_ack(&self) -> bool {
246        *self == Ibiresp::Ack
247    }
248    #[doc = "NACK (reject)"]
249    #[inline(always)]
250    pub fn is_nack(&self) -> bool {
251        *self == Ibiresp::Nack
252    }
253    #[doc = "Acknowledge with mandatory byte"]
254    #[inline(always)]
255    pub fn is_ack_with_mandatory(&self) -> bool {
256        *self == Ibiresp::AckWithMandatory
257    }
258    #[doc = "Manual"]
259    #[inline(always)]
260    pub fn is_manual(&self) -> bool {
261        *self == Ibiresp::Manual
262    }
263}
264#[doc = "Field `IBIRESP` writer - In-Band Interrupt Response"]
265pub type IbirespW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ibiresp, crate::Safe>;
266impl<'a, REG> IbirespW<'a, REG>
267where
268    REG: crate::Writable + crate::RegisterSpec,
269    REG::Ux: From<u8>,
270{
271    #[doc = "ACK (acknowledge)"]
272    #[inline(always)]
273    pub fn ack(self) -> &'a mut crate::W<REG> {
274        self.variant(Ibiresp::Ack)
275    }
276    #[doc = "NACK (reject)"]
277    #[inline(always)]
278    pub fn nack(self) -> &'a mut crate::W<REG> {
279        self.variant(Ibiresp::Nack)
280    }
281    #[doc = "Acknowledge with mandatory byte"]
282    #[inline(always)]
283    pub fn ack_with_mandatory(self) -> &'a mut crate::W<REG> {
284        self.variant(Ibiresp::AckWithMandatory)
285    }
286    #[doc = "Manual"]
287    #[inline(always)]
288    pub fn manual(self) -> &'a mut crate::W<REG> {
289        self.variant(Ibiresp::Manual)
290    }
291}
292#[doc = "Direction\n\nValue on reset: 0"]
293#[cfg_attr(feature = "defmt", derive(defmt::Format))]
294#[derive(Clone, Copy, Debug, PartialEq, Eq)]
295pub enum Dir {
296    #[doc = "0: Write"]
297    Dirwrite = 0,
298    #[doc = "1: Read"]
299    Dirread = 1,
300}
301impl From<Dir> for bool {
302    #[inline(always)]
303    fn from(variant: Dir) -> Self {
304        variant as u8 != 0
305    }
306}
307#[doc = "Field `DIR` reader - Direction"]
308pub type DirR = crate::BitReader<Dir>;
309impl DirR {
310    #[doc = "Get enumerated values variant"]
311    #[inline(always)]
312    pub const fn variant(&self) -> Dir {
313        match self.bits {
314            false => Dir::Dirwrite,
315            true => Dir::Dirread,
316        }
317    }
318    #[doc = "Write"]
319    #[inline(always)]
320    pub fn is_dirwrite(&self) -> bool {
321        *self == Dir::Dirwrite
322    }
323    #[doc = "Read"]
324    #[inline(always)]
325    pub fn is_dirread(&self) -> bool {
326        *self == Dir::Dirread
327    }
328}
329#[doc = "Field `DIR` writer - Direction"]
330pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>;
331impl<'a, REG> DirW<'a, REG>
332where
333    REG: crate::Writable + crate::RegisterSpec,
334{
335    #[doc = "Write"]
336    #[inline(always)]
337    pub fn dirwrite(self) -> &'a mut crate::W<REG> {
338        self.variant(Dir::Dirwrite)
339    }
340    #[doc = "Read"]
341    #[inline(always)]
342    pub fn dirread(self) -> &'a mut crate::W<REG> {
343        self.variant(Dir::Dirread)
344    }
345}
346#[doc = "Field `ADDR` reader - Address"]
347pub type AddrR = crate::FieldReader;
348#[doc = "Field `ADDR` writer - Address"]
349pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
350#[doc = "Field `RDTERM` reader - Read Terminate Counter"]
351pub type RdtermR = crate::FieldReader;
352#[doc = "Field `RDTERM` writer - Read Terminate Counter"]
353pub type RdtermW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
354impl R {
355    #[doc = "Bits 0:2 - Request"]
356    #[inline(always)]
357    pub fn request(&self) -> RequestR {
358        RequestR::new((self.bits & 7) as u8)
359    }
360    #[doc = "Bits 4:5 - Bus Type with EmitStartAddr"]
361    #[inline(always)]
362    pub fn type_(&self) -> TypeR {
363        TypeR::new(((self.bits >> 4) & 3) as u8)
364    }
365    #[doc = "Bits 6:7 - In-Band Interrupt Response"]
366    #[inline(always)]
367    pub fn ibiresp(&self) -> IbirespR {
368        IbirespR::new(((self.bits >> 6) & 3) as u8)
369    }
370    #[doc = "Bit 8 - Direction"]
371    #[inline(always)]
372    pub fn dir(&self) -> DirR {
373        DirR::new(((self.bits >> 8) & 1) != 0)
374    }
375    #[doc = "Bits 9:15 - Address"]
376    #[inline(always)]
377    pub fn addr(&self) -> AddrR {
378        AddrR::new(((self.bits >> 9) & 0x7f) as u8)
379    }
380    #[doc = "Bits 16:23 - Read Terminate Counter"]
381    #[inline(always)]
382    pub fn rdterm(&self) -> RdtermR {
383        RdtermR::new(((self.bits >> 16) & 0xff) as u8)
384    }
385}
386#[cfg(feature = "debug")]
387impl core::fmt::Debug for R {
388    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
389        f.debug_struct("MCTRL")
390            .field("request", &self.request())
391            .field("type_", &self.type_())
392            .field("ibiresp", &self.ibiresp())
393            .field("dir", &self.dir())
394            .field("addr", &self.addr())
395            .field("rdterm", &self.rdterm())
396            .finish()
397    }
398}
399impl W {
400    #[doc = "Bits 0:2 - Request"]
401    #[inline(always)]
402    pub fn request(&mut self) -> RequestW<'_, MctrlSpec> {
403        RequestW::new(self, 0)
404    }
405    #[doc = "Bits 4:5 - Bus Type with EmitStartAddr"]
406    #[inline(always)]
407    pub fn type_(&mut self) -> TypeW<'_, MctrlSpec> {
408        TypeW::new(self, 4)
409    }
410    #[doc = "Bits 6:7 - In-Band Interrupt Response"]
411    #[inline(always)]
412    pub fn ibiresp(&mut self) -> IbirespW<'_, MctrlSpec> {
413        IbirespW::new(self, 6)
414    }
415    #[doc = "Bit 8 - Direction"]
416    #[inline(always)]
417    pub fn dir(&mut self) -> DirW<'_, MctrlSpec> {
418        DirW::new(self, 8)
419    }
420    #[doc = "Bits 9:15 - Address"]
421    #[inline(always)]
422    pub fn addr(&mut self) -> AddrW<'_, MctrlSpec> {
423        AddrW::new(self, 9)
424    }
425    #[doc = "Bits 16:23 - Read Terminate Counter"]
426    #[inline(always)]
427    pub fn rdterm(&mut self) -> RdtermW<'_, MctrlSpec> {
428        RdtermW::new(self, 16)
429    }
430}
431#[doc = "Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
432pub struct MctrlSpec;
433impl crate::RegisterSpec for MctrlSpec {
434    type Ux = u32;
435}
436#[doc = "`read()` method returns [`mctrl::R`](R) reader structure"]
437impl crate::Readable for MctrlSpec {}
438#[doc = "`write(|w| ..)` method takes [`mctrl::W`](W) writer structure"]
439impl crate::Writable for MctrlSpec {
440    type Safety = crate::Unsafe;
441}
442#[doc = "`reset()` method sets MCTRL to value 0"]
443impl crate::Resettable for MctrlSpec {}
mcxa_pac/i3c0/mctrl.rs

mcxa_pac/i3c0/
mctrl.rs
