mcxa_pac/i3c0/
mconfig_ext.rs

1#[doc = "Register `MCONFIG_EXT` reader"]
2pub type R = crate::R<MconfigExtSpec>;
3#[doc = "Register `MCONFIG_EXT` writer"]
4pub type W = crate::W<MconfigExtSpec>;
5#[doc = "I3C CAS Delay After START\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum I3cCasDel {
10    #[doc = "0: No delay"]
11    NoDelay = 0,
12    #[doc = "1: Increases SCL clock period by 1/2"]
13    OneHalfClk = 1,
14    #[doc = "2: Increases SCL clock period by 1"]
15    OneClk = 2,
16    #[doc = "3: Increases SCL clock period by 3/2"]
17    OneAndOneHalfClk = 3,
18}
19impl From<I3cCasDel> for u8 {
20    #[inline(always)]
21    fn from(variant: I3cCasDel) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for I3cCasDel {
26    type Ux = u8;
27}
28impl crate::IsEnum for I3cCasDel {}
29#[doc = "Field `I3C_CAS_DEL` reader - I3C CAS Delay After START"]
30pub type I3cCasDelR = crate::FieldReader<I3cCasDel>;
31impl I3cCasDelR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> I3cCasDel {
35        match self.bits {
36            0 => I3cCasDel::NoDelay,
37            1 => I3cCasDel::OneHalfClk,
38            2 => I3cCasDel::OneClk,
39            3 => I3cCasDel::OneAndOneHalfClk,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "No delay"]
44    #[inline(always)]
45    pub fn is_no_delay(&self) -> bool {
46        *self == I3cCasDel::NoDelay
47    }
48    #[doc = "Increases SCL clock period by 1/2"]
49    #[inline(always)]
50    pub fn is_one_half_clk(&self) -> bool {
51        *self == I3cCasDel::OneHalfClk
52    }
53    #[doc = "Increases SCL clock period by 1"]
54    #[inline(always)]
55    pub fn is_one_clk(&self) -> bool {
56        *self == I3cCasDel::OneClk
57    }
58    #[doc = "Increases SCL clock period by 3/2"]
59    #[inline(always)]
60    pub fn is_one_and_one_half_clk(&self) -> bool {
61        *self == I3cCasDel::OneAndOneHalfClk
62    }
63}
64#[doc = "Field `I3C_CAS_DEL` writer - I3C CAS Delay After START"]
65pub type I3cCasDelW<'a, REG> = crate::FieldWriter<'a, REG, 2, I3cCasDel, crate::Safe>;
66impl<'a, REG> I3cCasDelW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "No delay"]
72    #[inline(always)]
73    pub fn no_delay(self) -> &'a mut crate::W<REG> {
74        self.variant(I3cCasDel::NoDelay)
75    }
76    #[doc = "Increases SCL clock period by 1/2"]
77    #[inline(always)]
78    pub fn one_half_clk(self) -> &'a mut crate::W<REG> {
79        self.variant(I3cCasDel::OneHalfClk)
80    }
81    #[doc = "Increases SCL clock period by 1"]
82    #[inline(always)]
83    pub fn one_clk(self) -> &'a mut crate::W<REG> {
84        self.variant(I3cCasDel::OneClk)
85    }
86    #[doc = "Increases SCL clock period by 3/2"]
87    #[inline(always)]
88    pub fn one_and_one_half_clk(self) -> &'a mut crate::W<REG> {
89        self.variant(I3cCasDel::OneAndOneHalfClk)
90    }
91}
92#[doc = "I3C CAS Delay After Repeated START\n\nValue on reset: 0"]
93#[cfg_attr(feature = "defmt", derive(defmt::Format))]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95#[repr(u8)]
96pub enum I3cCasrDel {
97    #[doc = "0: No delay"]
98    NoDelay = 0,
99    #[doc = "1: Increases SCL clock period by 1/2"]
100    OneHalfClk = 1,
101    #[doc = "2: Increases SCL clock period by 1"]
102    OneClk = 2,
103    #[doc = "3: Increases SCL clock period by 1 1/2"]
104    OneAndOneHalfClk = 3,
105}
106impl From<I3cCasrDel> for u8 {
107    #[inline(always)]
108    fn from(variant: I3cCasrDel) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for I3cCasrDel {
113    type Ux = u8;
114}
115impl crate::IsEnum for I3cCasrDel {}
116#[doc = "Field `I3C_CASR_DEL` reader - I3C CAS Delay After Repeated START"]
117pub type I3cCasrDelR = crate::FieldReader<I3cCasrDel>;
118impl I3cCasrDelR {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> I3cCasrDel {
122        match self.bits {
123            0 => I3cCasrDel::NoDelay,
124            1 => I3cCasrDel::OneHalfClk,
125            2 => I3cCasrDel::OneClk,
126            3 => I3cCasrDel::OneAndOneHalfClk,
127            _ => unreachable!(),
128        }
129    }
130    #[doc = "No delay"]
131    #[inline(always)]
132    pub fn is_no_delay(&self) -> bool {
133        *self == I3cCasrDel::NoDelay
134    }
135    #[doc = "Increases SCL clock period by 1/2"]
136    #[inline(always)]
137    pub fn is_one_half_clk(&self) -> bool {
138        *self == I3cCasrDel::OneHalfClk
139    }
140    #[doc = "Increases SCL clock period by 1"]
141    #[inline(always)]
142    pub fn is_one_clk(&self) -> bool {
143        *self == I3cCasrDel::OneClk
144    }
145    #[doc = "Increases SCL clock period by 1 1/2"]
146    #[inline(always)]
147    pub fn is_one_and_one_half_clk(&self) -> bool {
148        *self == I3cCasrDel::OneAndOneHalfClk
149    }
150}
151#[doc = "Field `I3C_CASR_DEL` writer - I3C CAS Delay After Repeated START"]
152pub type I3cCasrDelW<'a, REG> = crate::FieldWriter<'a, REG, 2, I3cCasrDel, crate::Safe>;
153impl<'a, REG> I3cCasrDelW<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "No delay"]
159    #[inline(always)]
160    pub fn no_delay(self) -> &'a mut crate::W<REG> {
161        self.variant(I3cCasrDel::NoDelay)
162    }
163    #[doc = "Increases SCL clock period by 1/2"]
164    #[inline(always)]
165    pub fn one_half_clk(self) -> &'a mut crate::W<REG> {
166        self.variant(I3cCasrDel::OneHalfClk)
167    }
168    #[doc = "Increases SCL clock period by 1"]
169    #[inline(always)]
170    pub fn one_clk(self) -> &'a mut crate::W<REG> {
171        self.variant(I3cCasrDel::OneClk)
172    }
173    #[doc = "Increases SCL clock period by 1 1/2"]
174    #[inline(always)]
175    pub fn one_and_one_half_clk(self) -> &'a mut crate::W<REG> {
176        self.variant(I3cCasrDel::OneAndOneHalfClk)
177    }
178}
179impl R {
180    #[doc = "Bits 16:17 - I3C CAS Delay After START"]
181    #[inline(always)]
182    pub fn i3c_cas_del(&self) -> I3cCasDelR {
183        I3cCasDelR::new(((self.bits >> 16) & 3) as u8)
184    }
185    #[doc = "Bits 18:19 - I3C CAS Delay After Repeated START"]
186    #[inline(always)]
187    pub fn i3c_casr_del(&self) -> I3cCasrDelR {
188        I3cCasrDelR::new(((self.bits >> 18) & 3) as u8)
189    }
190}
191#[cfg(feature = "debug")]
192impl core::fmt::Debug for R {
193    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
194        f.debug_struct("MCONFIG_EXT")
195            .field("i3c_cas_del", &self.i3c_cas_del())
196            .field("i3c_casr_del", &self.i3c_casr_del())
197            .finish()
198    }
199}
200impl W {
201    #[doc = "Bits 16:17 - I3C CAS Delay After START"]
202    #[inline(always)]
203    pub fn i3c_cas_del(&mut self) -> I3cCasDelW<'_, MconfigExtSpec> {
204        I3cCasDelW::new(self, 16)
205    }
206    #[doc = "Bits 18:19 - I3C CAS Delay After Repeated START"]
207    #[inline(always)]
208    pub fn i3c_casr_del(&mut self) -> I3cCasrDelW<'_, MconfigExtSpec> {
209        I3cCasrDelW::new(self, 18)
210    }
211}
212#[doc = "Controller Extended Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig_ext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig_ext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
213pub struct MconfigExtSpec;
214impl crate::RegisterSpec for MconfigExtSpec {
215    type Ux = u32;
216}
217#[doc = "`read()` method returns [`mconfig_ext::R`](R) reader structure"]
218impl crate::Readable for MconfigExtSpec {}
219#[doc = "`write(|w| ..)` method takes [`mconfig_ext::W`](W) writer structure"]
220impl crate::Writable for MconfigExtSpec {
221    type Safety = crate::Unsafe;
222}
223#[doc = "`reset()` method sets MCONFIG_EXT to value 0"]
224impl crate::Resettable for MconfigExtSpec {}
mcxa_pac/i3c0/mconfig_ext.rs

mcxa_pac/i3c0/
mconfig_ext.rs
