mcxa_pac/glikey0/
intr_ctrl.rs

1#[doc = "Register `INTR_CTRL` reader"]
2pub type R = crate::R<IntrCtrlSpec>;
3#[doc = "Register `INTR_CTRL` writer"]
4pub type W = crate::W<IntrCtrlSpec>;
5#[doc = "Field `INT_EN` reader - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"]
6pub type IntEnR = crate::BitReader;
7#[doc = "Field `INT_EN` writer - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"]
8pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `INT_CLR` reader - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"]
10pub type IntClrR = crate::BitReader;
11#[doc = "Field `INT_CLR` writer - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"]
12pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0\n\nValue on reset: 0"]
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16pub enum IntSet {
17    #[doc = "0: No effect"]
18    Disable = 0,
19    #[doc = "1: Triggers interrupt"]
20    Enable = 1,
21}
22impl From<IntSet> for bool {
23    #[inline(always)]
24    fn from(variant: IntSet) -> Self {
25        variant as u8 != 0
26    }
27}
28#[doc = "Field `INT_SET` reader - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"]
29pub type IntSetR = crate::BitReader<IntSet>;
30impl IntSetR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> IntSet {
34        match self.bits {
35            false => IntSet::Disable,
36            true => IntSet::Enable,
37        }
38    }
39    #[doc = "No effect"]
40    #[inline(always)]
41    pub fn is_disable(&self) -> bool {
42        *self == IntSet::Disable
43    }
44    #[doc = "Triggers interrupt"]
45    #[inline(always)]
46    pub fn is_enable(&self) -> bool {
47        *self == IntSet::Enable
48    }
49}
50#[doc = "Field `INT_SET` writer - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"]
51pub type IntSetW<'a, REG> = crate::BitWriter<'a, REG, IntSet>;
52impl<'a, REG> IntSetW<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55{
56    #[doc = "No effect"]
57    #[inline(always)]
58    pub fn disable(self) -> &'a mut crate::W<REG> {
59        self.variant(IntSet::Disable)
60    }
61    #[doc = "Triggers interrupt"]
62    #[inline(always)]
63    pub fn enable(self) -> &'a mut crate::W<REG> {
64        self.variant(IntSet::Enable)
65    }
66}
67#[doc = "Field `RESERVED31` reader - Reserved for Future Use"]
68pub type Reserved31R = crate::FieldReader<u32>;
69impl R {
70    #[doc = "Bit 0 - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"]
71    #[inline(always)]
72    pub fn int_en(&self) -> IntEnR {
73        IntEnR::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"]
76    #[inline(always)]
77    pub fn int_clr(&self) -> IntClrR {
78        IntClrR::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"]
81    #[inline(always)]
82    pub fn int_set(&self) -> IntSetR {
83        IntSetR::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bits 3:31 - Reserved for Future Use"]
86    #[inline(always)]
87    pub fn reserved31(&self) -> Reserved31R {
88        Reserved31R::new((self.bits >> 3) & 0x1fff_ffff)
89    }
90}
91#[cfg(feature = "debug")]
92impl core::fmt::Debug for R {
93    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
94        f.debug_struct("INTR_CTRL")
95            .field("int_en", &self.int_en())
96            .field("int_clr", &self.int_clr())
97            .field("int_set", &self.int_set())
98            .field("reserved31", &self.reserved31())
99            .finish()
100    }
101}
102impl W {
103    #[doc = "Bit 0 - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"]
104    #[inline(always)]
105    pub fn int_en(&mut self) -> IntEnW<'_, IntrCtrlSpec> {
106        IntEnW::new(self, 0)
107    }
108    #[doc = "Bit 1 - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"]
109    #[inline(always)]
110    pub fn int_clr(&mut self) -> IntClrW<'_, IntrCtrlSpec> {
111        IntClrW::new(self, 1)
112    }
113    #[doc = "Bit 2 - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"]
114    #[inline(always)]
115    pub fn int_set(&mut self) -> IntSetW<'_, IntrCtrlSpec> {
116        IntSetW::new(self, 2)
117    }
118}
119#[doc = "Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
120pub struct IntrCtrlSpec;
121impl crate::RegisterSpec for IntrCtrlSpec {
122    type Ux = u32;
123}
124#[doc = "`read()` method returns [`intr_ctrl::R`](R) reader structure"]
125impl crate::Readable for IntrCtrlSpec {}
126#[doc = "`write(|w| ..)` method takes [`intr_ctrl::W`](W) writer structure"]
127impl crate::Writable for IntrCtrlSpec {
128    type Safety = crate::Unsafe;
129}
130#[doc = "`reset()` method sets INTR_CTRL to value 0"]
131impl crate::Resettable for IntrCtrlSpec {}
mcxa_pac/glikey0/intr_ctrl.rs

mcxa_pac/glikey0/
intr_ctrl.rs
