mcxa_pac/flexpwm0/
sm3dismap0.rs

1#[doc = "Register `SM3DISMAP0` reader"]
2pub type R = crate::R<Sm3dismap0Spec>;
3#[doc = "Register `SM3DISMAP0` writer"]
4pub type W = crate::W<Sm3dismap0Spec>;
5#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"]
6pub type Dis0aR = crate::FieldReader;
7#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"]
8pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"]
10pub type Dis0bR = crate::FieldReader;
11#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"]
12pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"]
14pub type Dis0xR = crate::FieldReader;
15#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"]
16pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17impl R {
18    #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"]
19    #[inline(always)]
20    pub fn dis0a(&self) -> Dis0aR {
21        Dis0aR::new((self.bits & 0x0f) as u8)
22    }
23    #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"]
24    #[inline(always)]
25    pub fn dis0b(&self) -> Dis0bR {
26        Dis0bR::new(((self.bits >> 4) & 0x0f) as u8)
27    }
28    #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"]
29    #[inline(always)]
30    pub fn dis0x(&self) -> Dis0xR {
31        Dis0xR::new(((self.bits >> 8) & 0x0f) as u8)
32    }
33}
34#[cfg(feature = "debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("SM3DISMAP0")
38            .field("dis0a", &self.dis0a())
39            .field("dis0b", &self.dis0b())
40            .field("dis0x", &self.dis0x())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"]
46    #[inline(always)]
47    pub fn dis0a(&mut self) -> Dis0aW<'_, Sm3dismap0Spec> {
48        Dis0aW::new(self, 0)
49    }
50    #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"]
51    #[inline(always)]
52    pub fn dis0b(&mut self) -> Dis0bW<'_, Sm3dismap0Spec> {
53        Dis0bW::new(self, 4)
54    }
55    #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"]
56    #[inline(always)]
57    pub fn dis0x(&mut self) -> Dis0xW<'_, Sm3dismap0Spec> {
58        Dis0xW::new(self, 8)
59    }
60}
61#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct Sm3dismap0Spec;
63impl crate::RegisterSpec for Sm3dismap0Spec {
64    type Ux = u16;
65}
66#[doc = "`read()` method returns [`sm3dismap0::R`](R) reader structure"]
67impl crate::Readable for Sm3dismap0Spec {}
68#[doc = "`write(|w| ..)` method takes [`sm3dismap0::W`](W) writer structure"]
69impl crate::Writable for Sm3dismap0Spec {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets SM3DISMAP0 to value 0xffff"]
73impl crate::Resettable for Sm3dismap0Spec {
74    const RESET_VALUE: u16 = 0xffff;
75}
mcxa_pac/flexpwm0/sm3dismap0.rs

mcxa_pac/flexpwm0/
sm3dismap0.rs
