mcxa_pac/flexpwm0/
sm2cval0cyc.rs

1#[doc = "Register `SM2CVAL0CYC` reader"]
2pub type R = crate::R<Sm2cval0cycSpec>;
3#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"]
4pub type Cval0cycR = crate::FieldReader;
5impl R {
6    #[doc = "Bits 0:3 - Capture Value 0 Cycle"]
7    #[inline(always)]
8    pub fn cval0cyc(&self) -> Cval0cycR {
9        Cval0cycR::new((self.bits & 0x0f) as u8)
10    }
11}
12#[cfg(feature = "debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("SM2CVAL0CYC")
16            .field("cval0cyc", &self.cval0cyc())
17            .finish()
18    }
19}
20#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct Sm2cval0cycSpec;
22impl crate::RegisterSpec for Sm2cval0cycSpec {
23    type Ux = u16;
24}
25#[doc = "`read()` method returns [`sm2cval0cyc::R`](R) reader structure"]
26impl crate::Readable for Sm2cval0cycSpec {}
27#[doc = "`reset()` method sets SM2CVAL0CYC to value 0"]
28impl crate::Resettable for Sm2cval0cycSpec {}
mcxa_pac/flexpwm0/sm2cval0cyc.rs

mcxa_pac/flexpwm0/
sm2cval0cyc.rs
