mcxa_pac/flexpwm0/
sm1tctrl.rs

1#[doc = "Register `SM1TCTRL` reader"]
2pub type R = crate::R<Sm1tctrlSpec>;
3#[doc = "Register `SM1TCTRL` writer"]
4pub type W = crate::W<Sm1tctrlSpec>;
5#[doc = "Output Trigger Enables\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum OutTrigEn {
10    #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."]
11    Val0 = 1,
12}
13impl From<OutTrigEn> for u8 {
14    #[inline(always)]
15    fn from(variant: OutTrigEn) -> Self {
16        variant as _
17    }
18}
19impl crate::FieldSpec for OutTrigEn {
20    type Ux = u8;
21}
22impl crate::IsEnum for OutTrigEn {}
23#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"]
24pub type OutTrigEnR = crate::FieldReader<OutTrigEn>;
25impl OutTrigEnR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<OutTrigEn> {
29        match self.bits {
30            1 => Some(OutTrigEn::Val0),
31            _ => None,
32        }
33    }
34    #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."]
35    #[inline(always)]
36    pub fn is_val0(&self) -> bool {
37        *self == OutTrigEn::Val0
38    }
39}
40#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"]
41pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>;
42impl<'a, REG> OutTrigEnW<'a, REG>
43where
44    REG: crate::Writable + crate::RegisterSpec,
45    REG::Ux: From<u8>,
46{
47    #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."]
48    #[inline(always)]
49    pub fn val0(self) -> &'a mut crate::W<REG> {
50        self.variant(OutTrigEn::Val0)
51    }
52}
53#[doc = "Trigger Frequency\n\nValue on reset: 0"]
54#[cfg_attr(feature = "defmt", derive(defmt::Format))]
55#[derive(Clone, Copy, Debug, PartialEq, Eq)]
56pub enum Trgfrq {
57    #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
58    Everypwm = 0,
59    #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
60    Finalpwm = 1,
61}
62impl From<Trgfrq> for bool {
63    #[inline(always)]
64    fn from(variant: Trgfrq) -> Self {
65        variant as u8 != 0
66    }
67}
68#[doc = "Field `TRGFRQ` reader - Trigger Frequency"]
69pub type TrgfrqR = crate::BitReader<Trgfrq>;
70impl TrgfrqR {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub const fn variant(&self) -> Trgfrq {
74        match self.bits {
75            false => Trgfrq::Everypwm,
76            true => Trgfrq::Finalpwm,
77        }
78    }
79    #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
80    #[inline(always)]
81    pub fn is_everypwm(&self) -> bool {
82        *self == Trgfrq::Everypwm
83    }
84    #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
85    #[inline(always)]
86    pub fn is_finalpwm(&self) -> bool {
87        *self == Trgfrq::Finalpwm
88    }
89}
90#[doc = "Field `TRGFRQ` writer - Trigger Frequency"]
91pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>;
92impl<'a, REG> TrgfrqW<'a, REG>
93where
94    REG: crate::Writable + crate::RegisterSpec,
95{
96    #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
97    #[inline(always)]
98    pub fn everypwm(self) -> &'a mut crate::W<REG> {
99        self.variant(Trgfrq::Everypwm)
100    }
101    #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
102    #[inline(always)]
103    pub fn finalpwm(self) -> &'a mut crate::W<REG> {
104        self.variant(Trgfrq::Finalpwm)
105    }
106}
107#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"]
108#[cfg_attr(feature = "defmt", derive(defmt::Format))]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum Pwbot1 {
111    #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."]
112    PwmOutTrig1Signal = 0,
113    #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."]
114    PwmbOutput = 1,
115}
116impl From<Pwbot1> for bool {
117    #[inline(always)]
118    fn from(variant: Pwbot1) -> Self {
119        variant as u8 != 0
120    }
121}
122#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"]
123pub type Pwbot1R = crate::BitReader<Pwbot1>;
124impl Pwbot1R {
125    #[doc = "Get enumerated values variant"]
126    #[inline(always)]
127    pub const fn variant(&self) -> Pwbot1 {
128        match self.bits {
129            false => Pwbot1::PwmOutTrig1Signal,
130            true => Pwbot1::PwmbOutput,
131        }
132    }
133    #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."]
134    #[inline(always)]
135    pub fn is_pwm_out_trig1_signal(&self) -> bool {
136        *self == Pwbot1::PwmOutTrig1Signal
137    }
138    #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."]
139    #[inline(always)]
140    pub fn is_pwmb_output(&self) -> bool {
141        *self == Pwbot1::PwmbOutput
142    }
143}
144#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"]
145pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>;
146impl<'a, REG> Pwbot1W<'a, REG>
147where
148    REG: crate::Writable + crate::RegisterSpec,
149{
150    #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."]
151    #[inline(always)]
152    pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W<REG> {
153        self.variant(Pwbot1::PwmOutTrig1Signal)
154    }
155    #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."]
156    #[inline(always)]
157    pub fn pwmb_output(self) -> &'a mut crate::W<REG> {
158        self.variant(Pwbot1::PwmbOutput)
159    }
160}
161#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"]
162#[cfg_attr(feature = "defmt", derive(defmt::Format))]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum Pwaot0 {
165    #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."]
166    PwmOutTrig0Signal = 0,
167    #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."]
168    PwmaOutput = 1,
169}
170impl From<Pwaot0> for bool {
171    #[inline(always)]
172    fn from(variant: Pwaot0) -> Self {
173        variant as u8 != 0
174    }
175}
176#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"]
177pub type Pwaot0R = crate::BitReader<Pwaot0>;
178impl Pwaot0R {
179    #[doc = "Get enumerated values variant"]
180    #[inline(always)]
181    pub const fn variant(&self) -> Pwaot0 {
182        match self.bits {
183            false => Pwaot0::PwmOutTrig0Signal,
184            true => Pwaot0::PwmaOutput,
185        }
186    }
187    #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."]
188    #[inline(always)]
189    pub fn is_pwm_out_trig0_signal(&self) -> bool {
190        *self == Pwaot0::PwmOutTrig0Signal
191    }
192    #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."]
193    #[inline(always)]
194    pub fn is_pwma_output(&self) -> bool {
195        *self == Pwaot0::PwmaOutput
196    }
197}
198#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"]
199pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>;
200impl<'a, REG> Pwaot0W<'a, REG>
201where
202    REG: crate::Writable + crate::RegisterSpec,
203{
204    #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."]
205    #[inline(always)]
206    pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W<REG> {
207        self.variant(Pwaot0::PwmOutTrig0Signal)
208    }
209    #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."]
210    #[inline(always)]
211    pub fn pwma_output(self) -> &'a mut crate::W<REG> {
212        self.variant(Pwaot0::PwmaOutput)
213    }
214}
215impl R {
216    #[doc = "Bits 0:5 - Output Trigger Enables"]
217    #[inline(always)]
218    pub fn out_trig_en(&self) -> OutTrigEnR {
219        OutTrigEnR::new((self.bits & 0x3f) as u8)
220    }
221    #[doc = "Bit 12 - Trigger Frequency"]
222    #[inline(always)]
223    pub fn trgfrq(&self) -> TrgfrqR {
224        TrgfrqR::new(((self.bits >> 12) & 1) != 0)
225    }
226    #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"]
227    #[inline(always)]
228    pub fn pwbot1(&self) -> Pwbot1R {
229        Pwbot1R::new(((self.bits >> 14) & 1) != 0)
230    }
231    #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"]
232    #[inline(always)]
233    pub fn pwaot0(&self) -> Pwaot0R {
234        Pwaot0R::new(((self.bits >> 15) & 1) != 0)
235    }
236}
237#[cfg(feature = "debug")]
238impl core::fmt::Debug for R {
239    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
240        f.debug_struct("SM1TCTRL")
241            .field("out_trig_en", &self.out_trig_en())
242            .field("trgfrq", &self.trgfrq())
243            .field("pwbot1", &self.pwbot1())
244            .field("pwaot0", &self.pwaot0())
245            .finish()
246    }
247}
248impl W {
249    #[doc = "Bits 0:5 - Output Trigger Enables"]
250    #[inline(always)]
251    pub fn out_trig_en(&mut self) -> OutTrigEnW<'_, Sm1tctrlSpec> {
252        OutTrigEnW::new(self, 0)
253    }
254    #[doc = "Bit 12 - Trigger Frequency"]
255    #[inline(always)]
256    pub fn trgfrq(&mut self) -> TrgfrqW<'_, Sm1tctrlSpec> {
257        TrgfrqW::new(self, 12)
258    }
259    #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"]
260    #[inline(always)]
261    pub fn pwbot1(&mut self) -> Pwbot1W<'_, Sm1tctrlSpec> {
262        Pwbot1W::new(self, 14)
263    }
264    #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"]
265    #[inline(always)]
266    pub fn pwaot0(&mut self) -> Pwaot0W<'_, Sm1tctrlSpec> {
267        Pwaot0W::new(self, 15)
268    }
269}
270#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
271pub struct Sm1tctrlSpec;
272impl crate::RegisterSpec for Sm1tctrlSpec {
273    type Ux = u16;
274}
275#[doc = "`read()` method returns [`sm1tctrl::R`](R) reader structure"]
276impl crate::Readable for Sm1tctrlSpec {}
277#[doc = "`write(|w| ..)` method takes [`sm1tctrl::W`](W) writer structure"]
278impl crate::Writable for Sm1tctrlSpec {
279    type Safety = crate::Unsafe;
280}
281#[doc = "`reset()` method sets SM1TCTRL to value 0"]
282impl crate::Resettable for Sm1tctrlSpec {}
mcxa_pac/flexpwm0/sm1tctrl.rs

mcxa_pac/flexpwm0/
sm1tctrl.rs
