mcxa_pac/flexpwm0/
sm1phasedly.rs

1#[doc = "Register `SM1PHASEDLY` reader"]
2pub type R = crate::R<Sm1phasedlySpec>;
3#[doc = "Register `SM1PHASEDLY` writer"]
4pub type W = crate::W<Sm1phasedlySpec>;
5#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"]
6pub type PhasedlyR = crate::FieldReader<u16>;
7#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"]
8pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9impl R {
10    #[doc = "Bits 0:15 - Initial Count Register Bits"]
11    #[inline(always)]
12    pub fn phasedly(&self) -> PhasedlyR {
13        PhasedlyR::new(self.bits)
14    }
15}
16#[cfg(feature = "debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("SM1PHASEDLY")
20            .field("phasedly", &self.phasedly())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:15 - Initial Count Register Bits"]
26    #[inline(always)]
27    pub fn phasedly(&mut self) -> PhasedlyW<'_, Sm1phasedlySpec> {
28        PhasedlyW::new(self, 0)
29    }
30}
31#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct Sm1phasedlySpec;
33impl crate::RegisterSpec for Sm1phasedlySpec {
34    type Ux = u16;
35}
36#[doc = "`read()` method returns [`sm1phasedly::R`](R) reader structure"]
37impl crate::Readable for Sm1phasedlySpec {}
38#[doc = "`write(|w| ..)` method takes [`sm1phasedly::W`](W) writer structure"]
39impl crate::Writable for Sm1phasedlySpec {
40    type Safety = crate::Unsafe;
41}
42#[doc = "`reset()` method sets SM1PHASEDLY to value 0"]
43impl crate::Resettable for Sm1phasedlySpec {}
mcxa_pac/flexpwm0/sm1phasedly.rs

mcxa_pac/flexpwm0/
sm1phasedly.rs
