mcxa_pac/flexpwm0/
sm1dtcnt0.rs

1#[doc = "Register `SM1DTCNT0` reader"]
2pub type R = crate::R<Sm1dtcnt0Spec>;
3#[doc = "Register `SM1DTCNT0` writer"]
4pub type W = crate::W<Sm1dtcnt0Spec>;
5#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"]
6pub type Dtcnt0R = crate::FieldReader<u16>;
7#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"]
8pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
9impl R {
10    #[doc = "Bits 0:10 - Deadtime Count Register 0"]
11    #[inline(always)]
12    pub fn dtcnt0(&self) -> Dtcnt0R {
13        Dtcnt0R::new(self.bits & 0x07ff)
14    }
15}
16#[cfg(feature = "debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("SM1DTCNT0").field("dtcnt0", &self.dtcnt0()).finish()
20    }
21}
22impl W {
23    #[doc = "Bits 0:10 - Deadtime Count Register 0"]
24    #[inline(always)]
25    pub fn dtcnt0(&mut self) -> Dtcnt0W<'_, Sm1dtcnt0Spec> {
26        Dtcnt0W::new(self, 0)
27    }
28}
29#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct Sm1dtcnt0Spec;
31impl crate::RegisterSpec for Sm1dtcnt0Spec {
32    type Ux = u16;
33}
34#[doc = "`read()` method returns [`sm1dtcnt0::R`](R) reader structure"]
35impl crate::Readable for Sm1dtcnt0Spec {}
36#[doc = "`write(|w| ..)` method takes [`sm1dtcnt0::W`](W) writer structure"]
37impl crate::Writable for Sm1dtcnt0Spec {
38    type Safety = crate::Unsafe;
39}
40#[doc = "`reset()` method sets SM1DTCNT0 to value 0x07ff"]
41impl crate::Resettable for Sm1dtcnt0Spec {
42    const RESET_VALUE: u16 = 0x07ff;
43}
mcxa_pac/flexpwm0/sm1dtcnt0.rs

mcxa_pac/flexpwm0/
sm1dtcnt0.rs
