1#[doc = "Register `FCTRL0` reader"]
2pub type R = crate::R<Fctrl0Spec>;
3#[doc = "Register `FCTRL0` writer"]
4pub type W = crate::W<Fctrl0Spec>;
5#[doc = "Fault Interrupt Enables\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Fie {
10 #[doc = "0: FAULTx CPU interrupt requests disabled."]
11 Disabled = 0,
12 #[doc = "1: FAULTx CPU interrupt requests enabled."]
13 Enabled = 1,
14}
15impl From<Fie> for u8 {
16 #[inline(always)]
17 fn from(variant: Fie) -> Self {
18 variant as _
19 }
20}
21impl crate::FieldSpec for Fie {
22 type Ux = u8;
23}
24impl crate::IsEnum for Fie {}
25#[doc = "Field `FIE` reader - Fault Interrupt Enables"]
26pub type FieR = crate::FieldReader<Fie>;
27impl FieR {
28 #[doc = "Get enumerated values variant"]
29 #[inline(always)]
30 pub const fn variant(&self) -> Option<Fie> {
31 match self.bits {
32 0 => Some(Fie::Disabled),
33 1 => Some(Fie::Enabled),
34 _ => None,
35 }
36 }
37 #[doc = "FAULTx CPU interrupt requests disabled."]
38 #[inline(always)]
39 pub fn is_disabled(&self) -> bool {
40 *self == Fie::Disabled
41 }
42 #[doc = "FAULTx CPU interrupt requests enabled."]
43 #[inline(always)]
44 pub fn is_enabled(&self) -> bool {
45 *self == Fie::Enabled
46 }
47}
48#[doc = "Field `FIE` writer - Fault Interrupt Enables"]
49pub type FieW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fie>;
50impl<'a, REG> FieW<'a, REG>
51where
52 REG: crate::Writable + crate::RegisterSpec,
53 REG::Ux: From<u8>,
54{
55 #[doc = "FAULTx CPU interrupt requests disabled."]
56 #[inline(always)]
57 pub fn disabled(self) -> &'a mut crate::W<REG> {
58 self.variant(Fie::Disabled)
59 }
60 #[doc = "FAULTx CPU interrupt requests enabled."]
61 #[inline(always)]
62 pub fn enabled(self) -> &'a mut crate::W<REG> {
63 self.variant(Fie::Enabled)
64 }
65}
66#[doc = "Fault Safety Mode\n\nValue on reset: 0"]
67#[cfg_attr(feature = "defmt", derive(defmt::Format))]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69#[repr(u8)]
70pub enum Fsafe {
71 #[doc = "0: Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."]
72 Normal = 0,
73 #[doc = "1: Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."]
74 Safe = 1,
75}
76impl From<Fsafe> for u8 {
77 #[inline(always)]
78 fn from(variant: Fsafe) -> Self {
79 variant as _
80 }
81}
82impl crate::FieldSpec for Fsafe {
83 type Ux = u8;
84}
85impl crate::IsEnum for Fsafe {}
86#[doc = "Field `FSAFE` reader - Fault Safety Mode"]
87pub type FsafeR = crate::FieldReader<Fsafe>;
88impl FsafeR {
89 #[doc = "Get enumerated values variant"]
90 #[inline(always)]
91 pub const fn variant(&self) -> Option<Fsafe> {
92 match self.bits {
93 0 => Some(Fsafe::Normal),
94 1 => Some(Fsafe::Safe),
95 _ => None,
96 }
97 }
98 #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."]
99 #[inline(always)]
100 pub fn is_normal(&self) -> bool {
101 *self == Fsafe::Normal
102 }
103 #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."]
104 #[inline(always)]
105 pub fn is_safe(&self) -> bool {
106 *self == Fsafe::Safe
107 }
108}
109#[doc = "Field `FSAFE` writer - Fault Safety Mode"]
110pub type FsafeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fsafe>;
111impl<'a, REG> FsafeW<'a, REG>
112where
113 REG: crate::Writable + crate::RegisterSpec,
114 REG::Ux: From<u8>,
115{
116 #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."]
117 #[inline(always)]
118 pub fn normal(self) -> &'a mut crate::W<REG> {
119 self.variant(Fsafe::Normal)
120 }
121 #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."]
122 #[inline(always)]
123 pub fn safe(self) -> &'a mut crate::W<REG> {
124 self.variant(Fsafe::Safe)
125 }
126}
127#[doc = "Automatic Fault Clearing\n\nValue on reset: 0"]
128#[cfg_attr(feature = "defmt", derive(defmt::Format))]
129#[derive(Clone, Copy, Debug, PartialEq, Eq)]
130#[repr(u8)]
131pub enum Fauto {
132 #[doc = "0: Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."]
133 Manual = 0,
134 #[doc = "1: Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."]
135 Automatic = 1,
136}
137impl From<Fauto> for u8 {
138 #[inline(always)]
139 fn from(variant: Fauto) -> Self {
140 variant as _
141 }
142}
143impl crate::FieldSpec for Fauto {
144 type Ux = u8;
145}
146impl crate::IsEnum for Fauto {}
147#[doc = "Field `FAUTO` reader - Automatic Fault Clearing"]
148pub type FautoR = crate::FieldReader<Fauto>;
149impl FautoR {
150 #[doc = "Get enumerated values variant"]
151 #[inline(always)]
152 pub const fn variant(&self) -> Option<Fauto> {
153 match self.bits {
154 0 => Some(Fauto::Manual),
155 1 => Some(Fauto::Automatic),
156 _ => None,
157 }
158 }
159 #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."]
160 #[inline(always)]
161 pub fn is_manual(&self) -> bool {
162 *self == Fauto::Manual
163 }
164 #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."]
165 #[inline(always)]
166 pub fn is_automatic(&self) -> bool {
167 *self == Fauto::Automatic
168 }
169}
170#[doc = "Field `FAUTO` writer - Automatic Fault Clearing"]
171pub type FautoW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fauto>;
172impl<'a, REG> FautoW<'a, REG>
173where
174 REG: crate::Writable + crate::RegisterSpec,
175 REG::Ux: From<u8>,
176{
177 #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."]
178 #[inline(always)]
179 pub fn manual(self) -> &'a mut crate::W<REG> {
180 self.variant(Fauto::Manual)
181 }
182 #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."]
183 #[inline(always)]
184 pub fn automatic(self) -> &'a mut crate::W<REG> {
185 self.variant(Fauto::Automatic)
186 }
187}
188#[doc = "Fault Level\n\nValue on reset: 0"]
189#[cfg_attr(feature = "defmt", derive(defmt::Format))]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191#[repr(u8)]
192pub enum Flvl {
193 #[doc = "0: A logic 0 on the fault input indicates a fault condition."]
194 Logic0 = 0,
195 #[doc = "1: A logic 1 on the fault input indicates a fault condition."]
196 Logic1 = 1,
197}
198impl From<Flvl> for u8 {
199 #[inline(always)]
200 fn from(variant: Flvl) -> Self {
201 variant as _
202 }
203}
204impl crate::FieldSpec for Flvl {
205 type Ux = u8;
206}
207impl crate::IsEnum for Flvl {}
208#[doc = "Field `FLVL` reader - Fault Level"]
209pub type FlvlR = crate::FieldReader<Flvl>;
210impl FlvlR {
211 #[doc = "Get enumerated values variant"]
212 #[inline(always)]
213 pub const fn variant(&self) -> Option<Flvl> {
214 match self.bits {
215 0 => Some(Flvl::Logic0),
216 1 => Some(Flvl::Logic1),
217 _ => None,
218 }
219 }
220 #[doc = "A logic 0 on the fault input indicates a fault condition."]
221 #[inline(always)]
222 pub fn is_logic_0(&self) -> bool {
223 *self == Flvl::Logic0
224 }
225 #[doc = "A logic 1 on the fault input indicates a fault condition."]
226 #[inline(always)]
227 pub fn is_logic_1(&self) -> bool {
228 *self == Flvl::Logic1
229 }
230}
231#[doc = "Field `FLVL` writer - Fault Level"]
232pub type FlvlW<'a, REG> = crate::FieldWriter<'a, REG, 4, Flvl>;
233impl<'a, REG> FlvlW<'a, REG>
234where
235 REG: crate::Writable + crate::RegisterSpec,
236 REG::Ux: From<u8>,
237{
238 #[doc = "A logic 0 on the fault input indicates a fault condition."]
239 #[inline(always)]
240 pub fn logic_0(self) -> &'a mut crate::W<REG> {
241 self.variant(Flvl::Logic0)
242 }
243 #[doc = "A logic 1 on the fault input indicates a fault condition."]
244 #[inline(always)]
245 pub fn logic_1(self) -> &'a mut crate::W<REG> {
246 self.variant(Flvl::Logic1)
247 }
248}
249impl R {
250 #[doc = "Bits 0:3 - Fault Interrupt Enables"]
251 #[inline(always)]
252 pub fn fie(&self) -> FieR {
253 FieR::new((self.bits & 0x0f) as u8)
254 }
255 #[doc = "Bits 4:7 - Fault Safety Mode"]
256 #[inline(always)]
257 pub fn fsafe(&self) -> FsafeR {
258 FsafeR::new(((self.bits >> 4) & 0x0f) as u8)
259 }
260 #[doc = "Bits 8:11 - Automatic Fault Clearing"]
261 #[inline(always)]
262 pub fn fauto(&self) -> FautoR {
263 FautoR::new(((self.bits >> 8) & 0x0f) as u8)
264 }
265 #[doc = "Bits 12:15 - Fault Level"]
266 #[inline(always)]
267 pub fn flvl(&self) -> FlvlR {
268 FlvlR::new(((self.bits >> 12) & 0x0f) as u8)
269 }
270}
271#[cfg(feature = "debug")]
272impl core::fmt::Debug for R {
273 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
274 f.debug_struct("FCTRL0")
275 .field("fie", &self.fie())
276 .field("fsafe", &self.fsafe())
277 .field("fauto", &self.fauto())
278 .field("flvl", &self.flvl())
279 .finish()
280 }
281}
282impl W {
283 #[doc = "Bits 0:3 - Fault Interrupt Enables"]
284 #[inline(always)]
285 pub fn fie(&mut self) -> FieW<'_, Fctrl0Spec> {
286 FieW::new(self, 0)
287 }
288 #[doc = "Bits 4:7 - Fault Safety Mode"]
289 #[inline(always)]
290 pub fn fsafe(&mut self) -> FsafeW<'_, Fctrl0Spec> {
291 FsafeW::new(self, 4)
292 }
293 #[doc = "Bits 8:11 - Automatic Fault Clearing"]
294 #[inline(always)]
295 pub fn fauto(&mut self) -> FautoW<'_, Fctrl0Spec> {
296 FautoW::new(self, 8)
297 }
298 #[doc = "Bits 12:15 - Fault Level"]
299 #[inline(always)]
300 pub fn flvl(&mut self) -> FlvlW<'_, Fctrl0Spec> {
301 FlvlW::new(self, 12)
302 }
303}
304#[doc = "Fault Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
305pub struct Fctrl0Spec;
306impl crate::RegisterSpec for Fctrl0Spec {
307 type Ux = u16;
308}
309#[doc = "`read()` method returns [`fctrl0::R`](R) reader structure"]
310impl crate::Readable for Fctrl0Spec {}
311#[doc = "`write(|w| ..)` method takes [`fctrl0::W`](W) writer structure"]
312impl crate::Writable for Fctrl0Spec {
313 type Safety = crate::Unsafe;
314}
315#[doc = "`reset()` method sets FCTRL0 to value 0"]
316impl crate::Resettable for Fctrl0Spec {}