mcxa_pac/flexio0/
timstat.rs

1#[doc = "Register `TIMSTAT` reader"]
2pub type R = crate::R<TimstatSpec>;
3#[doc = "Register `TIMSTAT` writer"]
4pub type W = crate::W<TimstatSpec>;
5#[doc = "Timer Status Flag\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Tsf {
10    #[doc = "0: Clear"]
11    Clr = 0,
12    #[doc = "1: Set"]
13    Set = 1,
14}
15impl From<Tsf> for u8 {
16    #[inline(always)]
17    fn from(variant: Tsf) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Tsf {
22    type Ux = u8;
23}
24impl crate::IsEnum for Tsf {}
25#[doc = "Field `TSF` reader - Timer Status Flag"]
26pub type TsfR = crate::FieldReader<Tsf>;
27impl TsfR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Tsf> {
31        match self.bits {
32            0 => Some(Tsf::Clr),
33            1 => Some(Tsf::Set),
34            _ => None,
35        }
36    }
37    #[doc = "Clear"]
38    #[inline(always)]
39    pub fn is_clr(&self) -> bool {
40        *self == Tsf::Clr
41    }
42    #[doc = "Set"]
43    #[inline(always)]
44    pub fn is_set(&self) -> bool {
45        *self == Tsf::Set
46    }
47}
48#[doc = "Field `TSF` writer - Timer Status Flag"]
49pub type TsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Tsf>;
50impl<'a, REG> TsfW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u8>,
54{
55    #[doc = "Clear"]
56    #[inline(always)]
57    pub fn clr(self) -> &'a mut crate::W<REG> {
58        self.variant(Tsf::Clr)
59    }
60    #[doc = "Set"]
61    #[inline(always)]
62    pub fn set_(self) -> &'a mut crate::W<REG> {
63        self.variant(Tsf::Set)
64    }
65}
66impl R {
67    #[doc = "Bits 0:3 - Timer Status Flag"]
68    #[inline(always)]
69    pub fn tsf(&self) -> TsfR {
70        TsfR::new((self.bits & 0x0f) as u8)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("TIMSTAT").field("tsf", &self.tsf()).finish()
77    }
78}
79impl W {
80    #[doc = "Bits 0:3 - Timer Status Flag"]
81    #[inline(always)]
82    pub fn tsf(&mut self) -> TsfW<'_, TimstatSpec> {
83        TsfW::new(self, 0)
84    }
85}
86#[doc = "Timer Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`timstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct TimstatSpec;
88impl crate::RegisterSpec for TimstatSpec {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`timstat::R`](R) reader structure"]
92impl crate::Readable for TimstatSpec {}
93#[doc = "`write(|w| ..)` method takes [`timstat::W`](W) writer structure"]
94impl crate::Writable for TimstatSpec {
95    type Safety = crate::Unsafe;
96    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
97}
98#[doc = "`reset()` method sets TIMSTAT to value 0"]
99impl crate::Resettable for TimstatSpec {}
mcxa_pac/flexio0/timstat.rs

mcxa_pac/flexio0/
timstat.rs
