mcxa_pac/eqdc0/
filt.rs

1#[doc = "Register `FILT` reader"]
2pub type R = crate::R<FiltSpec>;
3#[doc = "Register `FILT` writer"]
4pub type W = crate::W<FiltSpec>;
5#[doc = "Field `FILT_PER` reader - Input Filter Sample Period"]
6pub type FiltPerR = crate::FieldReader;
7#[doc = "Field `FILT_PER` writer - Input Filter Sample Period"]
8pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `FILT_CNT` reader - Input Filter Sample Count"]
10pub type FiltCntR = crate::FieldReader;
11#[doc = "Field `FILT_CNT` writer - Input Filter Sample Count"]
12pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Filter Clock Source selection\n\nValue on reset: 0"]
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16pub enum FiltCs {
17    #[doc = "0: Peripheral Clock"]
18    FiltCs0 = 0,
19    #[doc = "1: Prescaled peripheral clock by PRSC"]
20    FiltCs1 = 1,
21}
22impl From<FiltCs> for bool {
23    #[inline(always)]
24    fn from(variant: FiltCs) -> Self {
25        variant as u8 != 0
26    }
27}
28#[doc = "Field `FILT_CS` reader - Filter Clock Source selection"]
29pub type FiltCsR = crate::BitReader<FiltCs>;
30impl FiltCsR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> FiltCs {
34        match self.bits {
35            false => FiltCs::FiltCs0,
36            true => FiltCs::FiltCs1,
37        }
38    }
39    #[doc = "Peripheral Clock"]
40    #[inline(always)]
41    pub fn is_filt_cs0(&self) -> bool {
42        *self == FiltCs::FiltCs0
43    }
44    #[doc = "Prescaled peripheral clock by PRSC"]
45    #[inline(always)]
46    pub fn is_filt_cs1(&self) -> bool {
47        *self == FiltCs::FiltCs1
48    }
49}
50#[doc = "Field `FILT_CS` writer - Filter Clock Source selection"]
51pub type FiltCsW<'a, REG> = crate::BitWriter<'a, REG, FiltCs>;
52impl<'a, REG> FiltCsW<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55{
56    #[doc = "Peripheral Clock"]
57    #[inline(always)]
58    pub fn filt_cs0(self) -> &'a mut crate::W<REG> {
59        self.variant(FiltCs::FiltCs0)
60    }
61    #[doc = "Prescaled peripheral clock by PRSC"]
62    #[inline(always)]
63    pub fn filt_cs1(self) -> &'a mut crate::W<REG> {
64        self.variant(FiltCs::FiltCs1)
65    }
66}
67#[doc = "Field `PRSC` reader - Prescaler"]
68pub type PrscR = crate::FieldReader;
69#[doc = "Field `PRSC` writer - Prescaler"]
70pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
71impl R {
72    #[doc = "Bits 0:7 - Input Filter Sample Period"]
73    #[inline(always)]
74    pub fn filt_per(&self) -> FiltPerR {
75        FiltPerR::new((self.bits & 0xff) as u8)
76    }
77    #[doc = "Bits 8:10 - Input Filter Sample Count"]
78    #[inline(always)]
79    pub fn filt_cnt(&self) -> FiltCntR {
80        FiltCntR::new(((self.bits >> 8) & 7) as u8)
81    }
82    #[doc = "Bit 11 - Filter Clock Source selection"]
83    #[inline(always)]
84    pub fn filt_cs(&self) -> FiltCsR {
85        FiltCsR::new(((self.bits >> 11) & 1) != 0)
86    }
87    #[doc = "Bits 12:15 - Prescaler"]
88    #[inline(always)]
89    pub fn prsc(&self) -> PrscR {
90        PrscR::new(((self.bits >> 12) & 0x0f) as u8)
91    }
92}
93#[cfg(feature = "debug")]
94impl core::fmt::Debug for R {
95    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
96        f.debug_struct("FILT")
97            .field("filt_per", &self.filt_per())
98            .field("filt_cnt", &self.filt_cnt())
99            .field("filt_cs", &self.filt_cs())
100            .field("prsc", &self.prsc())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bits 0:7 - Input Filter Sample Period"]
106    #[inline(always)]
107    pub fn filt_per(&mut self) -> FiltPerW<'_, FiltSpec> {
108        FiltPerW::new(self, 0)
109    }
110    #[doc = "Bits 8:10 - Input Filter Sample Count"]
111    #[inline(always)]
112    pub fn filt_cnt(&mut self) -> FiltCntW<'_, FiltSpec> {
113        FiltCntW::new(self, 8)
114    }
115    #[doc = "Bit 11 - Filter Clock Source selection"]
116    #[inline(always)]
117    pub fn filt_cs(&mut self) -> FiltCsW<'_, FiltSpec> {
118        FiltCsW::new(self, 11)
119    }
120    #[doc = "Bits 12:15 - Prescaler"]
121    #[inline(always)]
122    pub fn prsc(&mut self) -> PrscW<'_, FiltSpec> {
123        PrscW::new(self, 12)
124    }
125}
126#[doc = "Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
127pub struct FiltSpec;
128impl crate::RegisterSpec for FiltSpec {
129    type Ux = u16;
130}
131#[doc = "`read()` method returns [`filt::R`](R) reader structure"]
132impl crate::Readable for FiltSpec {}
133#[doc = "`write(|w| ..)` method takes [`filt::W`](W) writer structure"]
134impl crate::Writable for FiltSpec {
135    type Safety = crate::Unsafe;
136}
137#[doc = "`reset()` method sets FILT to value 0"]
138impl crate::Resettable for FiltSpec {}
mcxa_pac/eqdc0/filt.rs

mcxa_pac/eqdc0/
filt.rs
