mcxa_pac/eqdc0/
ctrl2.rs

1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<Ctrl2Spec>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<Ctrl2Spec>;
5#[doc = "Field `UPDHLD` reader - Update Hold Registers"]
6pub type UpdhldR = crate::BitReader;
7#[doc = "Field `UPDHLD` writer - Update Hold Registers"]
8pub type UpdhldW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `UPDPOS` reader - Update Position Registers"]
10pub type UpdposR = crate::BitReader;
11#[doc = "Field `UPDPOS` writer - Update Position Registers"]
12pub type UpdposW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operation Mode Select\n\nValue on reset: 0"]
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16pub enum Opmode {
17    #[doc = "0: Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."]
18    Opmode0 = 0,
19    #[doc = "1: Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."]
20    Opmode1 = 1,
21}
22impl From<Opmode> for bool {
23    #[inline(always)]
24    fn from(variant: Opmode) -> Self {
25        variant as u8 != 0
26    }
27}
28#[doc = "Field `OPMODE` reader - Operation Mode Select"]
29pub type OpmodeR = crate::BitReader<Opmode>;
30impl OpmodeR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Opmode {
34        match self.bits {
35            false => Opmode::Opmode0,
36            true => Opmode::Opmode1,
37        }
38    }
39    #[doc = "Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."]
40    #[inline(always)]
41    pub fn is_opmode0(&self) -> bool {
42        *self == Opmode::Opmode0
43    }
44    #[doc = "Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."]
45    #[inline(always)]
46    pub fn is_opmode1(&self) -> bool {
47        *self == Opmode::Opmode1
48    }
49}
50#[doc = "Field `OPMODE` writer - Operation Mode Select"]
51pub type OpmodeW<'a, REG> = crate::BitWriter<'a, REG, Opmode>;
52impl<'a, REG> OpmodeW<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55{
56    #[doc = "Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."]
57    #[inline(always)]
58    pub fn opmode0(self) -> &'a mut crate::W<REG> {
59        self.variant(Opmode::Opmode0)
60    }
61    #[doc = "Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."]
62    #[inline(always)]
63    pub fn opmode1(self) -> &'a mut crate::W<REG> {
64        self.variant(Opmode::Opmode1)
65    }
66}
67#[doc = "Buffered Register Load (Update) Mode Select\n\nValue on reset: 0"]
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum Ldmod {
71    #[doc = "0: Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."]
72    Ldmod0 = 0,
73    #[doc = "1: Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."]
74    Ldmod1 = 1,
75}
76impl From<Ldmod> for bool {
77    #[inline(always)]
78    fn from(variant: Ldmod) -> Self {
79        variant as u8 != 0
80    }
81}
82#[doc = "Field `LDMOD` reader - Buffered Register Load (Update) Mode Select"]
83pub type LdmodR = crate::BitReader<Ldmod>;
84impl LdmodR {
85    #[doc = "Get enumerated values variant"]
86    #[inline(always)]
87    pub const fn variant(&self) -> Ldmod {
88        match self.bits {
89            false => Ldmod::Ldmod0,
90            true => Ldmod::Ldmod1,
91        }
92    }
93    #[doc = "Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."]
94    #[inline(always)]
95    pub fn is_ldmod0(&self) -> bool {
96        *self == Ldmod::Ldmod0
97    }
98    #[doc = "Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."]
99    #[inline(always)]
100    pub fn is_ldmod1(&self) -> bool {
101        *self == Ldmod::Ldmod1
102    }
103}
104#[doc = "Field `LDMOD` writer - Buffered Register Load (Update) Mode Select"]
105pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>;
106impl<'a, REG> LdmodW<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    #[doc = "Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."]
111    #[inline(always)]
112    pub fn ldmod0(self) -> &'a mut crate::W<REG> {
113        self.variant(Ldmod::Ldmod0)
114    }
115    #[doc = "Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."]
116    #[inline(always)]
117    pub fn ldmod1(self) -> &'a mut crate::W<REG> {
118        self.variant(Ldmod::Ldmod1)
119    }
120}
121#[doc = "Revolution Counter Modulus Enable\n\nValue on reset: 0"]
122#[cfg_attr(feature = "defmt", derive(defmt::Format))]
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124pub enum Revmod {
125    #[doc = "0: Use INDEX pulse to increment/decrement revolution counter (REV)"]
126    Revmod0 = 0,
127    #[doc = "1: Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"]
128    Revmod1 = 1,
129}
130impl From<Revmod> for bool {
131    #[inline(always)]
132    fn from(variant: Revmod) -> Self {
133        variant as u8 != 0
134    }
135}
136#[doc = "Field `REVMOD` reader - Revolution Counter Modulus Enable"]
137pub type RevmodR = crate::BitReader<Revmod>;
138impl RevmodR {
139    #[doc = "Get enumerated values variant"]
140    #[inline(always)]
141    pub const fn variant(&self) -> Revmod {
142        match self.bits {
143            false => Revmod::Revmod0,
144            true => Revmod::Revmod1,
145        }
146    }
147    #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)"]
148    #[inline(always)]
149    pub fn is_revmod0(&self) -> bool {
150        *self == Revmod::Revmod0
151    }
152    #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"]
153    #[inline(always)]
154    pub fn is_revmod1(&self) -> bool {
155        *self == Revmod::Revmod1
156    }
157}
158#[doc = "Field `REVMOD` writer - Revolution Counter Modulus Enable"]
159pub type RevmodW<'a, REG> = crate::BitWriter<'a, REG, Revmod>;
160impl<'a, REG> RevmodW<'a, REG>
161where
162    REG: crate::Writable + crate::RegisterSpec,
163{
164    #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)"]
165    #[inline(always)]
166    pub fn revmod0(self) -> &'a mut crate::W<REG> {
167        self.variant(Revmod::Revmod0)
168    }
169    #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"]
170    #[inline(always)]
171    pub fn revmod1(self) -> &'a mut crate::W<REG> {
172        self.variant(Revmod::Revmod1)
173    }
174}
175#[doc = "Output Control\n\nValue on reset: 0"]
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum Outctl {
179    #[doc = "0: POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"]
180    Outctl0 = 0,
181    #[doc = "1: All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"]
182    Outctl1 = 1,
183}
184impl From<Outctl> for bool {
185    #[inline(always)]
186    fn from(variant: Outctl) -> Self {
187        variant as u8 != 0
188    }
189}
190#[doc = "Field `OUTCTL` reader - Output Control"]
191pub type OutctlR = crate::BitReader<Outctl>;
192impl OutctlR {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub const fn variant(&self) -> Outctl {
196        match self.bits {
197            false => Outctl::Outctl0,
198            true => Outctl::Outctl1,
199        }
200    }
201    #[doc = "POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"]
202    #[inline(always)]
203    pub fn is_outctl0(&self) -> bool {
204        *self == Outctl::Outctl0
205    }
206    #[doc = "All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"]
207    #[inline(always)]
208    pub fn is_outctl1(&self) -> bool {
209        *self == Outctl::Outctl1
210    }
211}
212#[doc = "Field `OUTCTL` writer - Output Control"]
213pub type OutctlW<'a, REG> = crate::BitWriter<'a, REG, Outctl>;
214impl<'a, REG> OutctlW<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    #[doc = "POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"]
219    #[inline(always)]
220    pub fn outctl0(self) -> &'a mut crate::W<REG> {
221        self.variant(Outctl::Outctl0)
222    }
223    #[doc = "All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"]
224    #[inline(always)]
225    pub fn outctl1(self) -> &'a mut crate::W<REG> {
226        self.variant(Outctl::Outctl1)
227    }
228}
229#[doc = "Period measurement function enable\n\nValue on reset: 0"]
230#[cfg_attr(feature = "defmt", derive(defmt::Format))]
231#[derive(Clone, Copy, Debug, PartialEq, Eq)]
232pub enum Pmen {
233    #[doc = "0: Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."]
234    Pmen0 = 0,
235    #[doc = "1: Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."]
236    Pmen1 = 1,
237}
238impl From<Pmen> for bool {
239    #[inline(always)]
240    fn from(variant: Pmen) -> Self {
241        variant as u8 != 0
242    }
243}
244#[doc = "Field `PMEN` reader - Period measurement function enable"]
245pub type PmenR = crate::BitReader<Pmen>;
246impl PmenR {
247    #[doc = "Get enumerated values variant"]
248    #[inline(always)]
249    pub const fn variant(&self) -> Pmen {
250        match self.bits {
251            false => Pmen::Pmen0,
252            true => Pmen::Pmen1,
253        }
254    }
255    #[doc = "Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."]
256    #[inline(always)]
257    pub fn is_pmen0(&self) -> bool {
258        *self == Pmen::Pmen0
259    }
260    #[doc = "Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."]
261    #[inline(always)]
262    pub fn is_pmen1(&self) -> bool {
263        *self == Pmen::Pmen1
264    }
265}
266#[doc = "Field `PMEN` writer - Period measurement function enable"]
267pub type PmenW<'a, REG> = crate::BitWriter<'a, REG, Pmen>;
268impl<'a, REG> PmenW<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271{
272    #[doc = "Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."]
273    #[inline(always)]
274    pub fn pmen0(self) -> &'a mut crate::W<REG> {
275        self.variant(Pmen::Pmen0)
276    }
277    #[doc = "Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."]
278    #[inline(always)]
279    pub fn pmen1(self) -> &'a mut crate::W<REG> {
280        self.variant(Pmen::Pmen1)
281    }
282}
283#[doc = "Enables/disables the position counter to be initialized by Index Event Edge Mark\n\nValue on reset: 0"]
284#[cfg_attr(feature = "defmt", derive(defmt::Format))]
285#[derive(Clone, Copy, Debug, PartialEq, Eq)]
286pub enum Emip {
287    #[doc = "0: disables the position counter to be initialized by Index Event Edge Mark"]
288    Emip0 = 0,
289    #[doc = "1: enables the position counter to be initialized by Index Event Edge Mark."]
290    Emip1 = 1,
291}
292impl From<Emip> for bool {
293    #[inline(always)]
294    fn from(variant: Emip) -> Self {
295        variant as u8 != 0
296    }
297}
298#[doc = "Field `EMIP` reader - Enables/disables the position counter to be initialized by Index Event Edge Mark"]
299pub type EmipR = crate::BitReader<Emip>;
300impl EmipR {
301    #[doc = "Get enumerated values variant"]
302    #[inline(always)]
303    pub const fn variant(&self) -> Emip {
304        match self.bits {
305            false => Emip::Emip0,
306            true => Emip::Emip1,
307        }
308    }
309    #[doc = "disables the position counter to be initialized by Index Event Edge Mark"]
310    #[inline(always)]
311    pub fn is_emip0(&self) -> bool {
312        *self == Emip::Emip0
313    }
314    #[doc = "enables the position counter to be initialized by Index Event Edge Mark."]
315    #[inline(always)]
316    pub fn is_emip1(&self) -> bool {
317        *self == Emip::Emip1
318    }
319}
320#[doc = "Field `EMIP` writer - Enables/disables the position counter to be initialized by Index Event Edge Mark"]
321pub type EmipW<'a, REG> = crate::BitWriter<'a, REG, Emip>;
322impl<'a, REG> EmipW<'a, REG>
323where
324    REG: crate::Writable + crate::RegisterSpec,
325{
326    #[doc = "disables the position counter to be initialized by Index Event Edge Mark"]
327    #[inline(always)]
328    pub fn emip0(self) -> &'a mut crate::W<REG> {
329        self.variant(Emip::Emip0)
330    }
331    #[doc = "enables the position counter to be initialized by Index Event Edge Mark."]
332    #[inline(always)]
333    pub fn emip1(self) -> &'a mut crate::W<REG> {
334        self.variant(Emip::Emip1)
335    }
336}
337#[doc = "Initial Position Register\n\nValue on reset: 0"]
338#[cfg_attr(feature = "defmt", derive(defmt::Format))]
339#[derive(Clone, Copy, Debug, PartialEq, Eq)]
340pub enum Initpos {
341    #[doc = "0: Don't initialize position counter on rising edge of TRIGGER"]
342    Initpos0 = 0,
343    #[doc = "1: Initialize position counter on rising edge of TRIGGER"]
344    Initpos1 = 1,
345}
346impl From<Initpos> for bool {
347    #[inline(always)]
348    fn from(variant: Initpos) -> Self {
349        variant as u8 != 0
350    }
351}
352#[doc = "Field `INITPOS` reader - Initial Position Register"]
353pub type InitposR = crate::BitReader<Initpos>;
354impl InitposR {
355    #[doc = "Get enumerated values variant"]
356    #[inline(always)]
357    pub const fn variant(&self) -> Initpos {
358        match self.bits {
359            false => Initpos::Initpos0,
360            true => Initpos::Initpos1,
361        }
362    }
363    #[doc = "Don't initialize position counter on rising edge of TRIGGER"]
364    #[inline(always)]
365    pub fn is_initpos0(&self) -> bool {
366        *self == Initpos::Initpos0
367    }
368    #[doc = "Initialize position counter on rising edge of TRIGGER"]
369    #[inline(always)]
370    pub fn is_initpos1(&self) -> bool {
371        *self == Initpos::Initpos1
372    }
373}
374#[doc = "Field `INITPOS` writer - Initial Position Register"]
375pub type InitposW<'a, REG> = crate::BitWriter<'a, REG, Initpos>;
376impl<'a, REG> InitposW<'a, REG>
377where
378    REG: crate::Writable + crate::RegisterSpec,
379{
380    #[doc = "Don't initialize position counter on rising edge of TRIGGER"]
381    #[inline(always)]
382    pub fn initpos0(self) -> &'a mut crate::W<REG> {
383        self.variant(Initpos::Initpos0)
384    }
385    #[doc = "Initialize position counter on rising edge of TRIGGER"]
386    #[inline(always)]
387    pub fn initpos1(self) -> &'a mut crate::W<REG> {
388        self.variant(Initpos::Initpos1)
389    }
390}
391#[doc = "Count Once\n\nValue on reset: 0"]
392#[cfg_attr(feature = "defmt", derive(defmt::Format))]
393#[derive(Clone, Copy, Debug, PartialEq, Eq)]
394pub enum Once {
395    #[doc = "0: Position counter counts repeatedly"]
396    Once0 = 0,
397    #[doc = "1: Position counter counts until roll-over or roll-under, then stop."]
398    Once1 = 1,
399}
400impl From<Once> for bool {
401    #[inline(always)]
402    fn from(variant: Once) -> Self {
403        variant as u8 != 0
404    }
405}
406#[doc = "Field `ONCE` reader - Count Once"]
407pub type OnceR = crate::BitReader<Once>;
408impl OnceR {
409    #[doc = "Get enumerated values variant"]
410    #[inline(always)]
411    pub const fn variant(&self) -> Once {
412        match self.bits {
413            false => Once::Once0,
414            true => Once::Once1,
415        }
416    }
417    #[doc = "Position counter counts repeatedly"]
418    #[inline(always)]
419    pub fn is_once0(&self) -> bool {
420        *self == Once::Once0
421    }
422    #[doc = "Position counter counts until roll-over or roll-under, then stop."]
423    #[inline(always)]
424    pub fn is_once1(&self) -> bool {
425        *self == Once::Once1
426    }
427}
428#[doc = "Field `ONCE` writer - Count Once"]
429pub type OnceW<'a, REG> = crate::BitWriter<'a, REG, Once>;
430impl<'a, REG> OnceW<'a, REG>
431where
432    REG: crate::Writable + crate::RegisterSpec,
433{
434    #[doc = "Position counter counts repeatedly"]
435    #[inline(always)]
436    pub fn once0(self) -> &'a mut crate::W<REG> {
437        self.variant(Once::Once0)
438    }
439    #[doc = "Position counter counts until roll-over or roll-under, then stop."]
440    #[inline(always)]
441    pub fn once1(self) -> &'a mut crate::W<REG> {
442        self.variant(Once::Once1)
443    }
444}
445#[doc = "Field `CMODE` reader - Counting Mode"]
446pub type CmodeR = crate::FieldReader;
447#[doc = "Field `CMODE` writer - Counting Mode"]
448pub type CmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
449impl R {
450    #[doc = "Bit 0 - Update Hold Registers"]
451    #[inline(always)]
452    pub fn updhld(&self) -> UpdhldR {
453        UpdhldR::new((self.bits & 1) != 0)
454    }
455    #[doc = "Bit 1 - Update Position Registers"]
456    #[inline(always)]
457    pub fn updpos(&self) -> UpdposR {
458        UpdposR::new(((self.bits >> 1) & 1) != 0)
459    }
460    #[doc = "Bit 2 - Operation Mode Select"]
461    #[inline(always)]
462    pub fn opmode(&self) -> OpmodeR {
463        OpmodeR::new(((self.bits >> 2) & 1) != 0)
464    }
465    #[doc = "Bit 3 - Buffered Register Load (Update) Mode Select"]
466    #[inline(always)]
467    pub fn ldmod(&self) -> LdmodR {
468        LdmodR::new(((self.bits >> 3) & 1) != 0)
469    }
470    #[doc = "Bit 8 - Revolution Counter Modulus Enable"]
471    #[inline(always)]
472    pub fn revmod(&self) -> RevmodR {
473        RevmodR::new(((self.bits >> 8) & 1) != 0)
474    }
475    #[doc = "Bit 9 - Output Control"]
476    #[inline(always)]
477    pub fn outctl(&self) -> OutctlR {
478        OutctlR::new(((self.bits >> 9) & 1) != 0)
479    }
480    #[doc = "Bit 10 - Period measurement function enable"]
481    #[inline(always)]
482    pub fn pmen(&self) -> PmenR {
483        PmenR::new(((self.bits >> 10) & 1) != 0)
484    }
485    #[doc = "Bit 11 - Enables/disables the position counter to be initialized by Index Event Edge Mark"]
486    #[inline(always)]
487    pub fn emip(&self) -> EmipR {
488        EmipR::new(((self.bits >> 11) & 1) != 0)
489    }
490    #[doc = "Bit 12 - Initial Position Register"]
491    #[inline(always)]
492    pub fn initpos(&self) -> InitposR {
493        InitposR::new(((self.bits >> 12) & 1) != 0)
494    }
495    #[doc = "Bit 13 - Count Once"]
496    #[inline(always)]
497    pub fn once(&self) -> OnceR {
498        OnceR::new(((self.bits >> 13) & 1) != 0)
499    }
500    #[doc = "Bits 14:15 - Counting Mode"]
501    #[inline(always)]
502    pub fn cmode(&self) -> CmodeR {
503        CmodeR::new(((self.bits >> 14) & 3) as u8)
504    }
505}
506#[cfg(feature = "debug")]
507impl core::fmt::Debug for R {
508    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
509        f.debug_struct("CTRL2")
510            .field("updhld", &self.updhld())
511            .field("updpos", &self.updpos())
512            .field("opmode", &self.opmode())
513            .field("ldmod", &self.ldmod())
514            .field("revmod", &self.revmod())
515            .field("outctl", &self.outctl())
516            .field("pmen", &self.pmen())
517            .field("emip", &self.emip())
518            .field("initpos", &self.initpos())
519            .field("once", &self.once())
520            .field("cmode", &self.cmode())
521            .finish()
522    }
523}
524impl W {
525    #[doc = "Bit 0 - Update Hold Registers"]
526    #[inline(always)]
527    pub fn updhld(&mut self) -> UpdhldW<'_, Ctrl2Spec> {
528        UpdhldW::new(self, 0)
529    }
530    #[doc = "Bit 1 - Update Position Registers"]
531    #[inline(always)]
532    pub fn updpos(&mut self) -> UpdposW<'_, Ctrl2Spec> {
533        UpdposW::new(self, 1)
534    }
535    #[doc = "Bit 2 - Operation Mode Select"]
536    #[inline(always)]
537    pub fn opmode(&mut self) -> OpmodeW<'_, Ctrl2Spec> {
538        OpmodeW::new(self, 2)
539    }
540    #[doc = "Bit 3 - Buffered Register Load (Update) Mode Select"]
541    #[inline(always)]
542    pub fn ldmod(&mut self) -> LdmodW<'_, Ctrl2Spec> {
543        LdmodW::new(self, 3)
544    }
545    #[doc = "Bit 8 - Revolution Counter Modulus Enable"]
546    #[inline(always)]
547    pub fn revmod(&mut self) -> RevmodW<'_, Ctrl2Spec> {
548        RevmodW::new(self, 8)
549    }
550    #[doc = "Bit 9 - Output Control"]
551    #[inline(always)]
552    pub fn outctl(&mut self) -> OutctlW<'_, Ctrl2Spec> {
553        OutctlW::new(self, 9)
554    }
555    #[doc = "Bit 10 - Period measurement function enable"]
556    #[inline(always)]
557    pub fn pmen(&mut self) -> PmenW<'_, Ctrl2Spec> {
558        PmenW::new(self, 10)
559    }
560    #[doc = "Bit 11 - Enables/disables the position counter to be initialized by Index Event Edge Mark"]
561    #[inline(always)]
562    pub fn emip(&mut self) -> EmipW<'_, Ctrl2Spec> {
563        EmipW::new(self, 11)
564    }
565    #[doc = "Bit 12 - Initial Position Register"]
566    #[inline(always)]
567    pub fn initpos(&mut self) -> InitposW<'_, Ctrl2Spec> {
568        InitposW::new(self, 12)
569    }
570    #[doc = "Bit 13 - Count Once"]
571    #[inline(always)]
572    pub fn once(&mut self) -> OnceW<'_, Ctrl2Spec> {
573        OnceW::new(self, 13)
574    }
575    #[doc = "Bits 14:15 - Counting Mode"]
576    #[inline(always)]
577    pub fn cmode(&mut self) -> CmodeW<'_, Ctrl2Spec> {
578        CmodeW::new(self, 14)
579    }
580}
581#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
582pub struct Ctrl2Spec;
583impl crate::RegisterSpec for Ctrl2Spec {
584    type Ux = u16;
585}
586#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
587impl crate::Readable for Ctrl2Spec {}
588#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
589impl crate::Writable for Ctrl2Spec {
590    type Safety = crate::Unsafe;
591}
592#[doc = "`reset()` method sets CTRL2 to value 0"]
593impl crate::Resettable for Ctrl2Spec {}
mcxa_pac/eqdc0/ctrl2.rs

mcxa_pac/eqdc0/
ctrl2.rs
