mcxa_pac/edma_0_tcd0/tcd/
tcd_csr.rs

1#[doc = "Register `TCD_CSR` reader"]
2pub type R = crate::R<TcdCsrSpec>;
3#[doc = "Register `TCD_CSR` writer"]
4pub type W = crate::W<TcdCsrSpec>;
5#[doc = "Channel Start\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Start {
9    #[doc = "0: Channel not explicitly started"]
10    ChannelNotStarted = 0,
11    #[doc = "1: Channel explicitly started via a software-initiated service request"]
12    ChannelStarted = 1,
13}
14impl From<Start> for bool {
15    #[inline(always)]
16    fn from(variant: Start) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `START` reader - Channel Start"]
21pub type StartR = crate::BitReader<Start>;
22impl StartR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Start {
26        match self.bits {
27            false => Start::ChannelNotStarted,
28            true => Start::ChannelStarted,
29        }
30    }
31    #[doc = "Channel not explicitly started"]
32    #[inline(always)]
33    pub fn is_channel_not_started(&self) -> bool {
34        *self == Start::ChannelNotStarted
35    }
36    #[doc = "Channel explicitly started via a software-initiated service request"]
37    #[inline(always)]
38    pub fn is_channel_started(&self) -> bool {
39        *self == Start::ChannelStarted
40    }
41}
42#[doc = "Field `START` writer - Channel Start"]
43pub type StartW<'a, REG> = crate::BitWriter<'a, REG, Start>;
44impl<'a, REG> StartW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Channel not explicitly started"]
49    #[inline(always)]
50    pub fn channel_not_started(self) -> &'a mut crate::W<REG> {
51        self.variant(Start::ChannelNotStarted)
52    }
53    #[doc = "Channel explicitly started via a software-initiated service request"]
54    #[inline(always)]
55    pub fn channel_started(self) -> &'a mut crate::W<REG> {
56        self.variant(Start::ChannelStarted)
57    }
58}
59#[doc = "Enable Interrupt If Major count complete\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Intmajor {
63    #[doc = "0: End-of-major loop interrupt disabled"]
64    Disable = 0,
65    #[doc = "1: End-of-major loop interrupt enabled"]
66    Enable = 1,
67}
68impl From<Intmajor> for bool {
69    #[inline(always)]
70    fn from(variant: Intmajor) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `INTMAJOR` reader - Enable Interrupt If Major count complete"]
75pub type IntmajorR = crate::BitReader<Intmajor>;
76impl IntmajorR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Intmajor {
80        match self.bits {
81            false => Intmajor::Disable,
82            true => Intmajor::Enable,
83        }
84    }
85    #[doc = "End-of-major loop interrupt disabled"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Intmajor::Disable
89    }
90    #[doc = "End-of-major loop interrupt enabled"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Intmajor::Enable
94    }
95}
96#[doc = "Field `INTMAJOR` writer - Enable Interrupt If Major count complete"]
97pub type IntmajorW<'a, REG> = crate::BitWriter<'a, REG, Intmajor>;
98impl<'a, REG> IntmajorW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "End-of-major loop interrupt disabled"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Intmajor::Disable)
106    }
107    #[doc = "End-of-major loop interrupt enabled"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Intmajor::Enable)
111    }
112}
113#[doc = "Enable Interrupt If Major Counter Half-complete\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Inthalf {
117    #[doc = "0: Halfway point interrupt disabled"]
118    Disable = 0,
119    #[doc = "1: Halfway point interrupt enabled"]
120    Enable = 1,
121}
122impl From<Inthalf> for bool {
123    #[inline(always)]
124    fn from(variant: Inthalf) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `INTHALF` reader - Enable Interrupt If Major Counter Half-complete"]
129pub type InthalfR = crate::BitReader<Inthalf>;
130impl InthalfR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Inthalf {
134        match self.bits {
135            false => Inthalf::Disable,
136            true => Inthalf::Enable,
137        }
138    }
139    #[doc = "Halfway point interrupt disabled"]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == Inthalf::Disable
143    }
144    #[doc = "Halfway point interrupt enabled"]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == Inthalf::Enable
148    }
149}
150#[doc = "Field `INTHALF` writer - Enable Interrupt If Major Counter Half-complete"]
151pub type InthalfW<'a, REG> = crate::BitWriter<'a, REG, Inthalf>;
152impl<'a, REG> InthalfW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Halfway point interrupt disabled"]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(Inthalf::Disable)
160    }
161    #[doc = "Halfway point interrupt enabled"]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(Inthalf::Enable)
165    }
166}
167#[doc = "Disable Request\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Dreq {
171    #[doc = "0: No operation"]
172    ChannelNotAffected = 0,
173    #[doc = "1: Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"]
174    ErqFieldClear = 1,
175}
176impl From<Dreq> for bool {
177    #[inline(always)]
178    fn from(variant: Dreq) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `DREQ` reader - Disable Request"]
183pub type DreqR = crate::BitReader<Dreq>;
184impl DreqR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Dreq {
188        match self.bits {
189            false => Dreq::ChannelNotAffected,
190            true => Dreq::ErqFieldClear,
191        }
192    }
193    #[doc = "No operation"]
194    #[inline(always)]
195    pub fn is_channel_not_affected(&self) -> bool {
196        *self == Dreq::ChannelNotAffected
197    }
198    #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"]
199    #[inline(always)]
200    pub fn is_erq_field_clear(&self) -> bool {
201        *self == Dreq::ErqFieldClear
202    }
203}
204#[doc = "Field `DREQ` writer - Disable Request"]
205pub type DreqW<'a, REG> = crate::BitWriter<'a, REG, Dreq>;
206impl<'a, REG> DreqW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "No operation"]
211    #[inline(always)]
212    pub fn channel_not_affected(self) -> &'a mut crate::W<REG> {
213        self.variant(Dreq::ChannelNotAffected)
214    }
215    #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"]
216    #[inline(always)]
217    pub fn erq_field_clear(self) -> &'a mut crate::W<REG> {
218        self.variant(Dreq::ErqFieldClear)
219    }
220}
221#[doc = "Enable Scatter/Gather Processing\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Esg {
225    #[doc = "0: Current channel's TCD is normal format"]
226    NormalFormat = 0,
227    #[doc = "1: Current channel's TCD specifies scatter/gather format."]
228    ScatterGatherFormat = 1,
229}
230impl From<Esg> for bool {
231    #[inline(always)]
232    fn from(variant: Esg) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `ESG` reader - Enable Scatter/Gather Processing"]
237pub type EsgR = crate::BitReader<Esg>;
238impl EsgR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Esg {
242        match self.bits {
243            false => Esg::NormalFormat,
244            true => Esg::ScatterGatherFormat,
245        }
246    }
247    #[doc = "Current channel's TCD is normal format"]
248    #[inline(always)]
249    pub fn is_normal_format(&self) -> bool {
250        *self == Esg::NormalFormat
251    }
252    #[doc = "Current channel's TCD specifies scatter/gather format."]
253    #[inline(always)]
254    pub fn is_scatter_gather_format(&self) -> bool {
255        *self == Esg::ScatterGatherFormat
256    }
257}
258#[doc = "Field `ESG` writer - Enable Scatter/Gather Processing"]
259pub type EsgW<'a, REG> = crate::BitWriter<'a, REG, Esg>;
260impl<'a, REG> EsgW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Current channel's TCD is normal format"]
265    #[inline(always)]
266    pub fn normal_format(self) -> &'a mut crate::W<REG> {
267        self.variant(Esg::NormalFormat)
268    }
269    #[doc = "Current channel's TCD specifies scatter/gather format."]
270    #[inline(always)]
271    pub fn scatter_gather_format(self) -> &'a mut crate::W<REG> {
272        self.variant(Esg::ScatterGatherFormat)
273    }
274}
275#[doc = "Enable Link When Major Loop Complete\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Majorelink {
279    #[doc = "0: Channel-to-channel linking disabled"]
280    Disable = 0,
281    #[doc = "1: Channel-to-channel linking enabled"]
282    Enable = 1,
283}
284impl From<Majorelink> for bool {
285    #[inline(always)]
286    fn from(variant: Majorelink) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `MAJORELINK` reader - Enable Link When Major Loop Complete"]
291pub type MajorelinkR = crate::BitReader<Majorelink>;
292impl MajorelinkR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Majorelink {
296        match self.bits {
297            false => Majorelink::Disable,
298            true => Majorelink::Enable,
299        }
300    }
301    #[doc = "Channel-to-channel linking disabled"]
302    #[inline(always)]
303    pub fn is_disable(&self) -> bool {
304        *self == Majorelink::Disable
305    }
306    #[doc = "Channel-to-channel linking enabled"]
307    #[inline(always)]
308    pub fn is_enable(&self) -> bool {
309        *self == Majorelink::Enable
310    }
311}
312#[doc = "Field `MAJORELINK` writer - Enable Link When Major Loop Complete"]
313pub type MajorelinkW<'a, REG> = crate::BitWriter<'a, REG, Majorelink>;
314impl<'a, REG> MajorelinkW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Channel-to-channel linking disabled"]
319    #[inline(always)]
320    pub fn disable(self) -> &'a mut crate::W<REG> {
321        self.variant(Majorelink::Disable)
322    }
323    #[doc = "Channel-to-channel linking enabled"]
324    #[inline(always)]
325    pub fn enable(self) -> &'a mut crate::W<REG> {
326        self.variant(Majorelink::Enable)
327    }
328}
329#[doc = "Enable End-Of-Packet Processing\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Eeop {
333    #[doc = "0: End-of-packet operation disabled"]
334    Disable = 0,
335    #[doc = "1: End-of-packet hardware input signal enabled"]
336    Enable = 1,
337}
338impl From<Eeop> for bool {
339    #[inline(always)]
340    fn from(variant: Eeop) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `EEOP` reader - Enable End-Of-Packet Processing"]
345pub type EeopR = crate::BitReader<Eeop>;
346impl EeopR {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Eeop {
350        match self.bits {
351            false => Eeop::Disable,
352            true => Eeop::Enable,
353        }
354    }
355    #[doc = "End-of-packet operation disabled"]
356    #[inline(always)]
357    pub fn is_disable(&self) -> bool {
358        *self == Eeop::Disable
359    }
360    #[doc = "End-of-packet hardware input signal enabled"]
361    #[inline(always)]
362    pub fn is_enable(&self) -> bool {
363        *self == Eeop::Enable
364    }
365}
366#[doc = "Field `EEOP` writer - Enable End-Of-Packet Processing"]
367pub type EeopW<'a, REG> = crate::BitWriter<'a, REG, Eeop>;
368impl<'a, REG> EeopW<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "End-of-packet operation disabled"]
373    #[inline(always)]
374    pub fn disable(self) -> &'a mut crate::W<REG> {
375        self.variant(Eeop::Disable)
376    }
377    #[doc = "End-of-packet hardware input signal enabled"]
378    #[inline(always)]
379    pub fn enable(self) -> &'a mut crate::W<REG> {
380        self.variant(Eeop::Enable)
381    }
382}
383#[doc = "Enable Store Destination Address\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum Esda {
387    #[doc = "0: Ability to store destination address to system memory disabled"]
388    Disable = 0,
389    #[doc = "1: Ability to store destination address to system memory enabled"]
390    Enable = 1,
391}
392impl From<Esda> for bool {
393    #[inline(always)]
394    fn from(variant: Esda) -> Self {
395        variant as u8 != 0
396    }
397}
398#[doc = "Field `ESDA` reader - Enable Store Destination Address"]
399pub type EsdaR = crate::BitReader<Esda>;
400impl EsdaR {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> Esda {
404        match self.bits {
405            false => Esda::Disable,
406            true => Esda::Enable,
407        }
408    }
409    #[doc = "Ability to store destination address to system memory disabled"]
410    #[inline(always)]
411    pub fn is_disable(&self) -> bool {
412        *self == Esda::Disable
413    }
414    #[doc = "Ability to store destination address to system memory enabled"]
415    #[inline(always)]
416    pub fn is_enable(&self) -> bool {
417        *self == Esda::Enable
418    }
419}
420#[doc = "Field `ESDA` writer - Enable Store Destination Address"]
421pub type EsdaW<'a, REG> = crate::BitWriter<'a, REG, Esda>;
422impl<'a, REG> EsdaW<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "Ability to store destination address to system memory disabled"]
427    #[inline(always)]
428    pub fn disable(self) -> &'a mut crate::W<REG> {
429        self.variant(Esda::Disable)
430    }
431    #[doc = "Ability to store destination address to system memory enabled"]
432    #[inline(always)]
433    pub fn enable(self) -> &'a mut crate::W<REG> {
434        self.variant(Esda::Enable)
435    }
436}
437#[doc = "Field `MAJORLINKCH` reader - Major Loop Link Channel Number"]
438pub type MajorlinkchR = crate::FieldReader;
439#[doc = "Field `MAJORLINKCH` writer - Major Loop Link Channel Number"]
440pub type MajorlinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
441#[doc = "Bandwidth Control\n\nValue on reset: 0"]
442#[cfg_attr(feature = "defmt", derive(defmt::Format))]
443#[derive(Clone, Copy, Debug, PartialEq, Eq)]
444#[repr(u8)]
445pub enum Bwc {
446    #[doc = "0: No eDMA engine stalls"]
447    NoStall = 0,
448    #[doc = "2: eDMA engine stalls for 4 cycles after each R/W"]
449    EngineStallsFour = 2,
450    #[doc = "3: eDMA engine stalls for 8 cycles after each R/W"]
451    EngineStallsEight = 3,
452}
453impl From<Bwc> for u8 {
454    #[inline(always)]
455    fn from(variant: Bwc) -> Self {
456        variant as _
457    }
458}
459impl crate::FieldSpec for Bwc {
460    type Ux = u8;
461}
462impl crate::IsEnum for Bwc {}
463#[doc = "Field `BWC` reader - Bandwidth Control"]
464pub type BwcR = crate::FieldReader<Bwc>;
465impl BwcR {
466    #[doc = "Get enumerated values variant"]
467    #[inline(always)]
468    pub const fn variant(&self) -> Option<Bwc> {
469        match self.bits {
470            0 => Some(Bwc::NoStall),
471            2 => Some(Bwc::EngineStallsFour),
472            3 => Some(Bwc::EngineStallsEight),
473            _ => None,
474        }
475    }
476    #[doc = "No eDMA engine stalls"]
477    #[inline(always)]
478    pub fn is_no_stall(&self) -> bool {
479        *self == Bwc::NoStall
480    }
481    #[doc = "eDMA engine stalls for 4 cycles after each R/W"]
482    #[inline(always)]
483    pub fn is_engine_stalls_four(&self) -> bool {
484        *self == Bwc::EngineStallsFour
485    }
486    #[doc = "eDMA engine stalls for 8 cycles after each R/W"]
487    #[inline(always)]
488    pub fn is_engine_stalls_eight(&self) -> bool {
489        *self == Bwc::EngineStallsEight
490    }
491}
492#[doc = "Field `BWC` writer - Bandwidth Control"]
493pub type BwcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bwc>;
494impl<'a, REG> BwcW<'a, REG>
495where
496    REG: crate::Writable + crate::RegisterSpec,
497    REG::Ux: From<u8>,
498{
499    #[doc = "No eDMA engine stalls"]
500    #[inline(always)]
501    pub fn no_stall(self) -> &'a mut crate::W<REG> {
502        self.variant(Bwc::NoStall)
503    }
504    #[doc = "eDMA engine stalls for 4 cycles after each R/W"]
505    #[inline(always)]
506    pub fn engine_stalls_four(self) -> &'a mut crate::W<REG> {
507        self.variant(Bwc::EngineStallsFour)
508    }
509    #[doc = "eDMA engine stalls for 8 cycles after each R/W"]
510    #[inline(always)]
511    pub fn engine_stalls_eight(self) -> &'a mut crate::W<REG> {
512        self.variant(Bwc::EngineStallsEight)
513    }
514}
515impl R {
516    #[doc = "Bit 0 - Channel Start"]
517    #[inline(always)]
518    pub fn start(&self) -> StartR {
519        StartR::new((self.bits & 1) != 0)
520    }
521    #[doc = "Bit 1 - Enable Interrupt If Major count complete"]
522    #[inline(always)]
523    pub fn intmajor(&self) -> IntmajorR {
524        IntmajorR::new(((self.bits >> 1) & 1) != 0)
525    }
526    #[doc = "Bit 2 - Enable Interrupt If Major Counter Half-complete"]
527    #[inline(always)]
528    pub fn inthalf(&self) -> InthalfR {
529        InthalfR::new(((self.bits >> 2) & 1) != 0)
530    }
531    #[doc = "Bit 3 - Disable Request"]
532    #[inline(always)]
533    pub fn dreq(&self) -> DreqR {
534        DreqR::new(((self.bits >> 3) & 1) != 0)
535    }
536    #[doc = "Bit 4 - Enable Scatter/Gather Processing"]
537    #[inline(always)]
538    pub fn esg(&self) -> EsgR {
539        EsgR::new(((self.bits >> 4) & 1) != 0)
540    }
541    #[doc = "Bit 5 - Enable Link When Major Loop Complete"]
542    #[inline(always)]
543    pub fn majorelink(&self) -> MajorelinkR {
544        MajorelinkR::new(((self.bits >> 5) & 1) != 0)
545    }
546    #[doc = "Bit 6 - Enable End-Of-Packet Processing"]
547    #[inline(always)]
548    pub fn eeop(&self) -> EeopR {
549        EeopR::new(((self.bits >> 6) & 1) != 0)
550    }
551    #[doc = "Bit 7 - Enable Store Destination Address"]
552    #[inline(always)]
553    pub fn esda(&self) -> EsdaR {
554        EsdaR::new(((self.bits >> 7) & 1) != 0)
555    }
556    #[doc = "Bits 8:10 - Major Loop Link Channel Number"]
557    #[inline(always)]
558    pub fn majorlinkch(&self) -> MajorlinkchR {
559        MajorlinkchR::new(((self.bits >> 8) & 7) as u8)
560    }
561    #[doc = "Bits 14:15 - Bandwidth Control"]
562    #[inline(always)]
563    pub fn bwc(&self) -> BwcR {
564        BwcR::new(((self.bits >> 14) & 3) as u8)
565    }
566}
567#[cfg(feature = "debug")]
568impl core::fmt::Debug for R {
569    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
570        f.debug_struct("TCD_CSR")
571            .field("start", &self.start())
572            .field("intmajor", &self.intmajor())
573            .field("inthalf", &self.inthalf())
574            .field("dreq", &self.dreq())
575            .field("esg", &self.esg())
576            .field("majorelink", &self.majorelink())
577            .field("eeop", &self.eeop())
578            .field("esda", &self.esda())
579            .field("majorlinkch", &self.majorlinkch())
580            .field("bwc", &self.bwc())
581            .finish()
582    }
583}
584impl W {
585    #[doc = "Bit 0 - Channel Start"]
586    #[inline(always)]
587    pub fn start(&mut self) -> StartW<'_, TcdCsrSpec> {
588        StartW::new(self, 0)
589    }
590    #[doc = "Bit 1 - Enable Interrupt If Major count complete"]
591    #[inline(always)]
592    pub fn intmajor(&mut self) -> IntmajorW<'_, TcdCsrSpec> {
593        IntmajorW::new(self, 1)
594    }
595    #[doc = "Bit 2 - Enable Interrupt If Major Counter Half-complete"]
596    #[inline(always)]
597    pub fn inthalf(&mut self) -> InthalfW<'_, TcdCsrSpec> {
598        InthalfW::new(self, 2)
599    }
600    #[doc = "Bit 3 - Disable Request"]
601    #[inline(always)]
602    pub fn dreq(&mut self) -> DreqW<'_, TcdCsrSpec> {
603        DreqW::new(self, 3)
604    }
605    #[doc = "Bit 4 - Enable Scatter/Gather Processing"]
606    #[inline(always)]
607    pub fn esg(&mut self) -> EsgW<'_, TcdCsrSpec> {
608        EsgW::new(self, 4)
609    }
610    #[doc = "Bit 5 - Enable Link When Major Loop Complete"]
611    #[inline(always)]
612    pub fn majorelink(&mut self) -> MajorelinkW<'_, TcdCsrSpec> {
613        MajorelinkW::new(self, 5)
614    }
615    #[doc = "Bit 6 - Enable End-Of-Packet Processing"]
616    #[inline(always)]
617    pub fn eeop(&mut self) -> EeopW<'_, TcdCsrSpec> {
618        EeopW::new(self, 6)
619    }
620    #[doc = "Bit 7 - Enable Store Destination Address"]
621    #[inline(always)]
622    pub fn esda(&mut self) -> EsdaW<'_, TcdCsrSpec> {
623        EsdaW::new(self, 7)
624    }
625    #[doc = "Bits 8:10 - Major Loop Link Channel Number"]
626    #[inline(always)]
627    pub fn majorlinkch(&mut self) -> MajorlinkchW<'_, TcdCsrSpec> {
628        MajorlinkchW::new(self, 8)
629    }
630    #[doc = "Bits 14:15 - Bandwidth Control"]
631    #[inline(always)]
632    pub fn bwc(&mut self) -> BwcW<'_, TcdCsrSpec> {
633        BwcW::new(self, 14)
634    }
635}
636#[doc = "TCD Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
637pub struct TcdCsrSpec;
638impl crate::RegisterSpec for TcdCsrSpec {
639    type Ux = u16;
640}
641#[doc = "`read()` method returns [`tcd_csr::R`](R) reader structure"]
642impl crate::Readable for TcdCsrSpec {}
643#[doc = "`write(|w| ..)` method takes [`tcd_csr::W`](W) writer structure"]
644impl crate::Writable for TcdCsrSpec {
645    type Safety = crate::Unsafe;
646}
647#[doc = "`reset()` method sets TCD_CSR to value 0"]
648impl crate::Resettable for TcdCsrSpec {}
mcxa_pac/edma_0_tcd0/tcd/tcd_csr.rs

mcxa_pac/edma_0_tcd0/tcd/
tcd_csr.rs
