mcxa_pac/edma_0_tcd0/tcd/
ch_csr.rs

1#[doc = "Register `CH_CSR` reader"]
2pub type R = crate::R<ChCsrSpec>;
3#[doc = "Register `CH_CSR` writer"]
4pub type W = crate::W<ChCsrSpec>;
5#[doc = "Enable DMA Request\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Erq {
9    #[doc = "0: DMA hardware request signal for corresponding channel disabled"]
10    Disable = 0,
11    #[doc = "1: DMA hardware request signal for corresponding channel enabled"]
12    Enable = 1,
13}
14impl From<Erq> for bool {
15    #[inline(always)]
16    fn from(variant: Erq) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `ERQ` reader - Enable DMA Request"]
21pub type ErqR = crate::BitReader<Erq>;
22impl ErqR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Erq {
26        match self.bits {
27            false => Erq::Disable,
28            true => Erq::Enable,
29        }
30    }
31    #[doc = "DMA hardware request signal for corresponding channel disabled"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Erq::Disable
35    }
36    #[doc = "DMA hardware request signal for corresponding channel enabled"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Erq::Enable
40    }
41}
42#[doc = "Field `ERQ` writer - Enable DMA Request"]
43pub type ErqW<'a, REG> = crate::BitWriter<'a, REG, Erq>;
44impl<'a, REG> ErqW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "DMA hardware request signal for corresponding channel disabled"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Erq::Disable)
52    }
53    #[doc = "DMA hardware request signal for corresponding channel enabled"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Erq::Enable)
57    }
58}
59#[doc = "Enable Asynchronous DMA Request\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Earq {
63    #[doc = "0: Disable asynchronous DMA request for the channel"]
64    Disable = 0,
65    #[doc = "1: Enable asynchronous DMA request for the channel"]
66    Enable = 1,
67}
68impl From<Earq> for bool {
69    #[inline(always)]
70    fn from(variant: Earq) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `EARQ` reader - Enable Asynchronous DMA Request"]
75pub type EarqR = crate::BitReader<Earq>;
76impl EarqR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Earq {
80        match self.bits {
81            false => Earq::Disable,
82            true => Earq::Enable,
83        }
84    }
85    #[doc = "Disable asynchronous DMA request for the channel"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Earq::Disable
89    }
90    #[doc = "Enable asynchronous DMA request for the channel"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Earq::Enable
94    }
95}
96#[doc = "Field `EARQ` writer - Enable Asynchronous DMA Request"]
97pub type EarqW<'a, REG> = crate::BitWriter<'a, REG, Earq>;
98impl<'a, REG> EarqW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable asynchronous DMA request for the channel"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Earq::Disable)
106    }
107    #[doc = "Enable asynchronous DMA request for the channel"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Earq::Enable)
111    }
112}
113#[doc = "Enable Error Interrupt\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Eei {
117    #[doc = "0: Error signal for corresponding channel does not generate error interrupt"]
118    NoError = 0,
119    #[doc = "1: Assertion of error signal for corresponding channel generates error interrupt request"]
120    Error = 1,
121}
122impl From<Eei> for bool {
123    #[inline(always)]
124    fn from(variant: Eei) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `EEI` reader - Enable Error Interrupt"]
129pub type EeiR = crate::BitReader<Eei>;
130impl EeiR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Eei {
134        match self.bits {
135            false => Eei::NoError,
136            true => Eei::Error,
137        }
138    }
139    #[doc = "Error signal for corresponding channel does not generate error interrupt"]
140    #[inline(always)]
141    pub fn is_no_error(&self) -> bool {
142        *self == Eei::NoError
143    }
144    #[doc = "Assertion of error signal for corresponding channel generates error interrupt request"]
145    #[inline(always)]
146    pub fn is_error(&self) -> bool {
147        *self == Eei::Error
148    }
149}
150#[doc = "Field `EEI` writer - Enable Error Interrupt"]
151pub type EeiW<'a, REG> = crate::BitWriter<'a, REG, Eei>;
152impl<'a, REG> EeiW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Error signal for corresponding channel does not generate error interrupt"]
157    #[inline(always)]
158    pub fn no_error(self) -> &'a mut crate::W<REG> {
159        self.variant(Eei::NoError)
160    }
161    #[doc = "Assertion of error signal for corresponding channel generates error interrupt request"]
162    #[inline(always)]
163    pub fn error(self) -> &'a mut crate::W<REG> {
164        self.variant(Eei::Error)
165    }
166}
167#[doc = "Enable Buffered Writes\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Ebw {
171    #[doc = "0: Buffered writes on system bus disabled"]
172    Disable = 0,
173    #[doc = "1: Buffered writes on system bus enabled"]
174    Enable = 1,
175}
176impl From<Ebw> for bool {
177    #[inline(always)]
178    fn from(variant: Ebw) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `EBW` reader - Enable Buffered Writes"]
183pub type EbwR = crate::BitReader<Ebw>;
184impl EbwR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Ebw {
188        match self.bits {
189            false => Ebw::Disable,
190            true => Ebw::Enable,
191        }
192    }
193    #[doc = "Buffered writes on system bus disabled"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == Ebw::Disable
197    }
198    #[doc = "Buffered writes on system bus enabled"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == Ebw::Enable
202    }
203}
204#[doc = "Field `EBW` writer - Enable Buffered Writes"]
205pub type EbwW<'a, REG> = crate::BitWriter<'a, REG, Ebw>;
206impl<'a, REG> EbwW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Buffered writes on system bus disabled"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(Ebw::Disable)
214    }
215    #[doc = "Buffered writes on system bus enabled"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(Ebw::Enable)
219    }
220}
221#[doc = "Field `DONE` reader - Channel Done"]
222pub type DoneR = crate::BitReader;
223#[doc = "Field `DONE` writer - Channel Done"]
224pub type DoneW<'a, REG> = crate::BitWriter1C<'a, REG>;
225#[doc = "Field `ACTIVE` reader - Channel Active"]
226pub type ActiveR = crate::BitReader;
227impl R {
228    #[doc = "Bit 0 - Enable DMA Request"]
229    #[inline(always)]
230    pub fn erq(&self) -> ErqR {
231        ErqR::new((self.bits & 1) != 0)
232    }
233    #[doc = "Bit 1 - Enable Asynchronous DMA Request"]
234    #[inline(always)]
235    pub fn earq(&self) -> EarqR {
236        EarqR::new(((self.bits >> 1) & 1) != 0)
237    }
238    #[doc = "Bit 2 - Enable Error Interrupt"]
239    #[inline(always)]
240    pub fn eei(&self) -> EeiR {
241        EeiR::new(((self.bits >> 2) & 1) != 0)
242    }
243    #[doc = "Bit 3 - Enable Buffered Writes"]
244    #[inline(always)]
245    pub fn ebw(&self) -> EbwR {
246        EbwR::new(((self.bits >> 3) & 1) != 0)
247    }
248    #[doc = "Bit 30 - Channel Done"]
249    #[inline(always)]
250    pub fn done(&self) -> DoneR {
251        DoneR::new(((self.bits >> 30) & 1) != 0)
252    }
253    #[doc = "Bit 31 - Channel Active"]
254    #[inline(always)]
255    pub fn active(&self) -> ActiveR {
256        ActiveR::new(((self.bits >> 31) & 1) != 0)
257    }
258}
259#[cfg(feature = "debug")]
260impl core::fmt::Debug for R {
261    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
262        f.debug_struct("CH_CSR")
263            .field("erq", &self.erq())
264            .field("earq", &self.earq())
265            .field("eei", &self.eei())
266            .field("ebw", &self.ebw())
267            .field("done", &self.done())
268            .field("active", &self.active())
269            .finish()
270    }
271}
272impl W {
273    #[doc = "Bit 0 - Enable DMA Request"]
274    #[inline(always)]
275    pub fn erq(&mut self) -> ErqW<'_, ChCsrSpec> {
276        ErqW::new(self, 0)
277    }
278    #[doc = "Bit 1 - Enable Asynchronous DMA Request"]
279    #[inline(always)]
280    pub fn earq(&mut self) -> EarqW<'_, ChCsrSpec> {
281        EarqW::new(self, 1)
282    }
283    #[doc = "Bit 2 - Enable Error Interrupt"]
284    #[inline(always)]
285    pub fn eei(&mut self) -> EeiW<'_, ChCsrSpec> {
286        EeiW::new(self, 2)
287    }
288    #[doc = "Bit 3 - Enable Buffered Writes"]
289    #[inline(always)]
290    pub fn ebw(&mut self) -> EbwW<'_, ChCsrSpec> {
291        EbwW::new(self, 3)
292    }
293    #[doc = "Bit 30 - Channel Done"]
294    #[inline(always)]
295    pub fn done(&mut self) -> DoneW<'_, ChCsrSpec> {
296        DoneW::new(self, 30)
297    }
298}
299#[doc = "Channel Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
300pub struct ChCsrSpec;
301impl crate::RegisterSpec for ChCsrSpec {
302    type Ux = u32;
303}
304#[doc = "`read()` method returns [`ch_csr::R`](R) reader structure"]
305impl crate::Readable for ChCsrSpec {}
306#[doc = "`write(|w| ..)` method takes [`ch_csr::W`](W) writer structure"]
307impl crate::Writable for ChCsrSpec {
308    type Safety = crate::Unsafe;
309    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000_0000;
310}
311#[doc = "`reset()` method sets CH_CSR to value 0"]
312impl crate::Resettable for ChCsrSpec {}
mcxa_pac/edma_0_tcd0/tcd/ch_csr.rs

mcxa_pac/edma_0_tcd0/tcd/
ch_csr.rs
