mcxa_pac/can0/
mb10_32b_cs.rs

1#[doc = "Register `MB10_32B_CS` reader"]
2pub type R = crate::R<Mb10_32bCsSpec>;
3#[doc = "Register `MB10_32B_CS` writer"]
4pub type W = crate::W<Mb10_32bCsSpec>;
5#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6pub type TimeStampR = crate::FieldReader<u16>;
7#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."]
10pub type DlcR = crate::FieldReader;
11#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."]
12pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."]
14pub type RtrR = crate::BitReader;
15#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."]
16pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."]
18pub type IdeR = crate::BitReader;
19#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."]
20pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."]
22pub type SrrR = crate::BitReader;
23#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."]
24pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
26pub type CodeR = crate::FieldReader;
27#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
28pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
30pub type EsiR = crate::BitReader;
31#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
32pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
34pub type BrsR = crate::BitReader;
35#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
36pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
38pub type EdlR = crate::BitReader;
39#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
40pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
43    #[inline(always)]
44    pub fn time_stamp(&self) -> TimeStampR {
45        TimeStampR::new((self.bits & 0xffff) as u16)
46    }
47    #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."]
48    #[inline(always)]
49    pub fn dlc(&self) -> DlcR {
50        DlcR::new(((self.bits >> 16) & 0x0f) as u8)
51    }
52    #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."]
53    #[inline(always)]
54    pub fn rtr(&self) -> RtrR {
55        RtrR::new(((self.bits >> 20) & 1) != 0)
56    }
57    #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."]
58    #[inline(always)]
59    pub fn ide(&self) -> IdeR {
60        IdeR::new(((self.bits >> 21) & 1) != 0)
61    }
62    #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."]
63    #[inline(always)]
64    pub fn srr(&self) -> SrrR {
65        SrrR::new(((self.bits >> 22) & 1) != 0)
66    }
67    #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
68    #[inline(always)]
69    pub fn code(&self) -> CodeR {
70        CodeR::new(((self.bits >> 24) & 0x0f) as u8)
71    }
72    #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
73    #[inline(always)]
74    pub fn esi(&self) -> EsiR {
75        EsiR::new(((self.bits >> 29) & 1) != 0)
76    }
77    #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
78    #[inline(always)]
79    pub fn brs(&self) -> BrsR {
80        BrsR::new(((self.bits >> 30) & 1) != 0)
81    }
82    #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
83    #[inline(always)]
84    pub fn edl(&self) -> EdlR {
85        EdlR::new(((self.bits >> 31) & 1) != 0)
86    }
87}
88#[cfg(feature = "debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("MB10_32B_CS")
92            .field("time_stamp", &self.time_stamp())
93            .field("dlc", &self.dlc())
94            .field("rtr", &self.rtr())
95            .field("ide", &self.ide())
96            .field("srr", &self.srr())
97            .field("code", &self.code())
98            .field("esi", &self.esi())
99            .field("brs", &self.brs())
100            .field("edl", &self.edl())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
106    #[inline(always)]
107    pub fn time_stamp(&mut self) -> TimeStampW<'_, Mb10_32bCsSpec> {
108        TimeStampW::new(self, 0)
109    }
110    #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."]
111    #[inline(always)]
112    pub fn dlc(&mut self) -> DlcW<'_, Mb10_32bCsSpec> {
113        DlcW::new(self, 16)
114    }
115    #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."]
116    #[inline(always)]
117    pub fn rtr(&mut self) -> RtrW<'_, Mb10_32bCsSpec> {
118        RtrW::new(self, 20)
119    }
120    #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."]
121    #[inline(always)]
122    pub fn ide(&mut self) -> IdeW<'_, Mb10_32bCsSpec> {
123        IdeW::new(self, 21)
124    }
125    #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."]
126    #[inline(always)]
127    pub fn srr(&mut self) -> SrrW<'_, Mb10_32bCsSpec> {
128        SrrW::new(self, 22)
129    }
130    #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
131    #[inline(always)]
132    pub fn code(&mut self) -> CodeW<'_, Mb10_32bCsSpec> {
133        CodeW::new(self, 24)
134    }
135    #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
136    #[inline(always)]
137    pub fn esi(&mut self) -> EsiW<'_, Mb10_32bCsSpec> {
138        EsiW::new(self, 29)
139    }
140    #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
141    #[inline(always)]
142    pub fn brs(&mut self) -> BrsW<'_, Mb10_32bCsSpec> {
143        BrsW::new(self, 30)
144    }
145    #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
146    #[inline(always)]
147    pub fn edl(&mut self) -> EdlW<'_, Mb10_32bCsSpec> {
148        EdlW::new(self, 31)
149    }
150}
151#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb10_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb10_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct Mb10_32bCsSpec;
153impl crate::RegisterSpec for Mb10_32bCsSpec {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`mb10_32b_cs::R`](R) reader structure"]
157impl crate::Readable for Mb10_32bCsSpec {}
158#[doc = "`write(|w| ..)` method takes [`mb10_32b_cs::W`](W) writer structure"]
159impl crate::Writable for Mb10_32bCsSpec {
160    type Safety = crate::Unsafe;
161}
162#[doc = "`reset()` method sets MB10_32B_CS to value 0"]
163impl crate::Resettable for Mb10_32bCsSpec {}
mcxa_pac/can0/mb10_32b_cs.rs

mcxa_pac/can0/
mb10_32b_cs.rs
