mcxa_pac/can0/
iflag1.rs

1#[doc = "Register `IFLAG1` reader"]
2pub type R = crate::R<Iflag1Spec>;
3#[doc = "Register `IFLAG1` writer"]
4pub type W = crate::W<Iflag1Spec>;
5#[doc = "Buffer MB0 Interrupt or Clear Legacy FIFO bit\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Buf0i {
9    #[doc = "0: MB0 has no occurrence of successfully completed transmission or reception."]
10    BufferTxRxNotComplete = 0,
11    #[doc = "1: MB0 has successfully completed transmission or reception."]
12    BufferTxRxComplete = 1,
13}
14impl From<Buf0i> for bool {
15    #[inline(always)]
16    fn from(variant: Buf0i) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `BUF0I` reader - Buffer MB0 Interrupt or Clear Legacy FIFO bit"]
21pub type Buf0iR = crate::BitReader<Buf0i>;
22impl Buf0iR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Buf0i {
26        match self.bits {
27            false => Buf0i::BufferTxRxNotComplete,
28            true => Buf0i::BufferTxRxComplete,
29        }
30    }
31    #[doc = "MB0 has no occurrence of successfully completed transmission or reception."]
32    #[inline(always)]
33    pub fn is_buffer_tx_rx_not_complete(&self) -> bool {
34        *self == Buf0i::BufferTxRxNotComplete
35    }
36    #[doc = "MB0 has successfully completed transmission or reception."]
37    #[inline(always)]
38    pub fn is_buffer_tx_rx_complete(&self) -> bool {
39        *self == Buf0i::BufferTxRxComplete
40    }
41}
42#[doc = "Field `BUF0I` writer - Buffer MB0 Interrupt or Clear Legacy FIFO bit"]
43pub type Buf0iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf0i>;
44impl<'a, REG> Buf0iW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "MB0 has no occurrence of successfully completed transmission or reception."]
49    #[inline(always)]
50    pub fn buffer_tx_rx_not_complete(self) -> &'a mut crate::W<REG> {
51        self.variant(Buf0i::BufferTxRxNotComplete)
52    }
53    #[doc = "MB0 has successfully completed transmission or reception."]
54    #[inline(always)]
55    pub fn buffer_tx_rx_complete(self) -> &'a mut crate::W<REG> {
56        self.variant(Buf0i::BufferTxRxComplete)
57    }
58}
59#[doc = "Field `BUF4TO1I` reader - Buffer MBi Interrupt or Reserved"]
60pub type Buf4to1iR = crate::FieldReader;
61#[doc = "Field `BUF4TO1I` writer - Buffer MBi Interrupt or Reserved"]
62pub type Buf4to1iW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
63#[doc = "Buffer MB5 Interrupt or Frames available in Legacy RX FIFO\n\nValue on reset: 0"]
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum Buf5i {
67    #[doc = "0: No occurrence of completed transmission or reception, or no frames available"]
68    Id1 = 0,
69    #[doc = "1: MB5 completed transmission or reception, or frames available"]
70    Id2 = 1,
71}
72impl From<Buf5i> for bool {
73    #[inline(always)]
74    fn from(variant: Buf5i) -> Self {
75        variant as u8 != 0
76    }
77}
78#[doc = "Field `BUF5I` reader - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"]
79pub type Buf5iR = crate::BitReader<Buf5i>;
80impl Buf5iR {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub const fn variant(&self) -> Buf5i {
84        match self.bits {
85            false => Buf5i::Id1,
86            true => Buf5i::Id2,
87        }
88    }
89    #[doc = "No occurrence of completed transmission or reception, or no frames available"]
90    #[inline(always)]
91    pub fn is_id1(&self) -> bool {
92        *self == Buf5i::Id1
93    }
94    #[doc = "MB5 completed transmission or reception, or frames available"]
95    #[inline(always)]
96    pub fn is_id2(&self) -> bool {
97        *self == Buf5i::Id2
98    }
99}
100#[doc = "Field `BUF5I` writer - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"]
101pub type Buf5iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf5i>;
102impl<'a, REG> Buf5iW<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    #[doc = "No occurrence of completed transmission or reception, or no frames available"]
107    #[inline(always)]
108    pub fn id1(self) -> &'a mut crate::W<REG> {
109        self.variant(Buf5i::Id1)
110    }
111    #[doc = "MB5 completed transmission or reception, or frames available"]
112    #[inline(always)]
113    pub fn id2(self) -> &'a mut crate::W<REG> {
114        self.variant(Buf5i::Id2)
115    }
116}
117#[doc = "Buffer MB6 Interrupt or Legacy RX FIFO Warning\n\nValue on reset: 0"]
118#[cfg_attr(feature = "defmt", derive(defmt::Format))]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120pub enum Buf6i {
121    #[doc = "0: No occurrence of MB6 completing transmission or reception, or FIFO not almost full."]
122    Id1 = 0,
123    #[doc = "1: MB6 completed transmission or reception, or FIFO almost full."]
124    Id2 = 1,
125}
126impl From<Buf6i> for bool {
127    #[inline(always)]
128    fn from(variant: Buf6i) -> Self {
129        variant as u8 != 0
130    }
131}
132#[doc = "Field `BUF6I` reader - Buffer MB6 Interrupt or Legacy RX FIFO Warning"]
133pub type Buf6iR = crate::BitReader<Buf6i>;
134impl Buf6iR {
135    #[doc = "Get enumerated values variant"]
136    #[inline(always)]
137    pub const fn variant(&self) -> Buf6i {
138        match self.bits {
139            false => Buf6i::Id1,
140            true => Buf6i::Id2,
141        }
142    }
143    #[doc = "No occurrence of MB6 completing transmission or reception, or FIFO not almost full."]
144    #[inline(always)]
145    pub fn is_id1(&self) -> bool {
146        *self == Buf6i::Id1
147    }
148    #[doc = "MB6 completed transmission or reception, or FIFO almost full."]
149    #[inline(always)]
150    pub fn is_id2(&self) -> bool {
151        *self == Buf6i::Id2
152    }
153}
154#[doc = "Field `BUF6I` writer - Buffer MB6 Interrupt or Legacy RX FIFO Warning"]
155pub type Buf6iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf6i>;
156impl<'a, REG> Buf6iW<'a, REG>
157where
158    REG: crate::Writable + crate::RegisterSpec,
159{
160    #[doc = "No occurrence of MB6 completing transmission or reception, or FIFO not almost full."]
161    #[inline(always)]
162    pub fn id1(self) -> &'a mut crate::W<REG> {
163        self.variant(Buf6i::Id1)
164    }
165    #[doc = "MB6 completed transmission or reception, or FIFO almost full."]
166    #[inline(always)]
167    pub fn id2(self) -> &'a mut crate::W<REG> {
168        self.variant(Buf6i::Id2)
169    }
170}
171#[doc = "Buffer MB7 Interrupt or Legacy RX FIFO Overflow\n\nValue on reset: 0"]
172#[cfg_attr(feature = "defmt", derive(defmt::Format))]
173#[derive(Clone, Copy, Debug, PartialEq, Eq)]
174pub enum Buf7i {
175    #[doc = "0: No occurrence of MB7 completing transmission or reception, or no FIFO overflow."]
176    Id1 = 0,
177    #[doc = "1: MB7 completed transmission or reception, or FIFO overflow."]
178    Id2 = 1,
179}
180impl From<Buf7i> for bool {
181    #[inline(always)]
182    fn from(variant: Buf7i) -> Self {
183        variant as u8 != 0
184    }
185}
186#[doc = "Field `BUF7I` reader - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"]
187pub type Buf7iR = crate::BitReader<Buf7i>;
188impl Buf7iR {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> Buf7i {
192        match self.bits {
193            false => Buf7i::Id1,
194            true => Buf7i::Id2,
195        }
196    }
197    #[doc = "No occurrence of MB7 completing transmission or reception, or no FIFO overflow."]
198    #[inline(always)]
199    pub fn is_id1(&self) -> bool {
200        *self == Buf7i::Id1
201    }
202    #[doc = "MB7 completed transmission or reception, or FIFO overflow."]
203    #[inline(always)]
204    pub fn is_id2(&self) -> bool {
205        *self == Buf7i::Id2
206    }
207}
208#[doc = "Field `BUF7I` writer - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"]
209pub type Buf7iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf7i>;
210impl<'a, REG> Buf7iW<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "No occurrence of MB7 completing transmission or reception, or no FIFO overflow."]
215    #[inline(always)]
216    pub fn id1(self) -> &'a mut crate::W<REG> {
217        self.variant(Buf7i::Id1)
218    }
219    #[doc = "MB7 completed transmission or reception, or FIFO overflow."]
220    #[inline(always)]
221    pub fn id2(self) -> &'a mut crate::W<REG> {
222        self.variant(Buf7i::Id2)
223    }
224}
225#[doc = "Field `BUF31TO8I` reader - Buffer MBi Interrupt"]
226pub type Buf31to8iR = crate::FieldReader<u32>;
227#[doc = "Field `BUF31TO8I` writer - Buffer MBi Interrupt"]
228pub type Buf31to8iW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
229impl R {
230    #[doc = "Bit 0 - Buffer MB0 Interrupt or Clear Legacy FIFO bit"]
231    #[inline(always)]
232    pub fn buf0i(&self) -> Buf0iR {
233        Buf0iR::new((self.bits & 1) != 0)
234    }
235    #[doc = "Bits 1:4 - Buffer MBi Interrupt or Reserved"]
236    #[inline(always)]
237    pub fn buf4to1i(&self) -> Buf4to1iR {
238        Buf4to1iR::new(((self.bits >> 1) & 0x0f) as u8)
239    }
240    #[doc = "Bit 5 - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"]
241    #[inline(always)]
242    pub fn buf5i(&self) -> Buf5iR {
243        Buf5iR::new(((self.bits >> 5) & 1) != 0)
244    }
245    #[doc = "Bit 6 - Buffer MB6 Interrupt or Legacy RX FIFO Warning"]
246    #[inline(always)]
247    pub fn buf6i(&self) -> Buf6iR {
248        Buf6iR::new(((self.bits >> 6) & 1) != 0)
249    }
250    #[doc = "Bit 7 - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"]
251    #[inline(always)]
252    pub fn buf7i(&self) -> Buf7iR {
253        Buf7iR::new(((self.bits >> 7) & 1) != 0)
254    }
255    #[doc = "Bits 8:31 - Buffer MBi Interrupt"]
256    #[inline(always)]
257    pub fn buf31to8i(&self) -> Buf31to8iR {
258        Buf31to8iR::new((self.bits >> 8) & 0x00ff_ffff)
259    }
260}
261#[cfg(feature = "debug")]
262impl core::fmt::Debug for R {
263    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
264        f.debug_struct("IFLAG1")
265            .field("buf0i", &self.buf0i())
266            .field("buf4to1i", &self.buf4to1i())
267            .field("buf5i", &self.buf5i())
268            .field("buf6i", &self.buf6i())
269            .field("buf7i", &self.buf7i())
270            .field("buf31to8i", &self.buf31to8i())
271            .finish()
272    }
273}
274impl W {
275    #[doc = "Bit 0 - Buffer MB0 Interrupt or Clear Legacy FIFO bit"]
276    #[inline(always)]
277    pub fn buf0i(&mut self) -> Buf0iW<'_, Iflag1Spec> {
278        Buf0iW::new(self, 0)
279    }
280    #[doc = "Bits 1:4 - Buffer MBi Interrupt or Reserved"]
281    #[inline(always)]
282    pub fn buf4to1i(&mut self) -> Buf4to1iW<'_, Iflag1Spec> {
283        Buf4to1iW::new(self, 1)
284    }
285    #[doc = "Bit 5 - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"]
286    #[inline(always)]
287    pub fn buf5i(&mut self) -> Buf5iW<'_, Iflag1Spec> {
288        Buf5iW::new(self, 5)
289    }
290    #[doc = "Bit 6 - Buffer MB6 Interrupt or Legacy RX FIFO Warning"]
291    #[inline(always)]
292    pub fn buf6i(&mut self) -> Buf6iW<'_, Iflag1Spec> {
293        Buf6iW::new(self, 6)
294    }
295    #[doc = "Bit 7 - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"]
296    #[inline(always)]
297    pub fn buf7i(&mut self) -> Buf7iW<'_, Iflag1Spec> {
298        Buf7iW::new(self, 7)
299    }
300    #[doc = "Bits 8:31 - Buffer MBi Interrupt"]
301    #[inline(always)]
302    pub fn buf31to8i(&mut self) -> Buf31to8iW<'_, Iflag1Spec> {
303        Buf31to8iW::new(self, 8)
304    }
305}
306#[doc = "Interrupt Flags 1\n\nYou can [`read`](crate::Reg::read) this register and get [`iflag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iflag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
307pub struct Iflag1Spec;
308impl crate::RegisterSpec for Iflag1Spec {
309    type Ux = u32;
310}
311#[doc = "`read()` method returns [`iflag1::R`](R) reader structure"]
312impl crate::Readable for Iflag1Spec {}
313#[doc = "`write(|w| ..)` method takes [`iflag1::W`](W) writer structure"]
314impl crate::Writable for Iflag1Spec {
315    type Safety = crate::Unsafe;
316    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff;
317}
318#[doc = "`reset()` method sets IFLAG1 to value 0"]
319impl crate::Resettable for Iflag1Spec {}
mcxa_pac/can0/iflag1.rs

mcxa_pac/can0/
iflag1.rs
