1#[doc = "Register `FDC` reader"]
2pub type R = crate::R<FdcSpec>;
3#[doc = "Register `FDC` writer"]
4pub type W = crate::W<FdcSpec>;
5#[doc = "Filter Configuration for FILTn\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Filtc1 {
10 #[doc = "0: Interrupt"]
11 Interrupt = 0,
12 #[doc = "1: DMA request"]
13 DmaReq = 1,
14 #[doc = "2: Trigger event"]
15 Trigger = 2,
16}
17impl From<Filtc1> for u8 {
18 #[inline(always)]
19 fn from(variant: Filtc1) -> Self {
20 variant as _
21 }
22}
23impl crate::FieldSpec for Filtc1 {
24 type Ux = u8;
25}
26impl crate::IsEnum for Filtc1 {}
27#[doc = "Field `FILTC1` reader - Filter Configuration for FILTn"]
28pub type Filtc1R = crate::FieldReader<Filtc1>;
29impl Filtc1R {
30 #[doc = "Get enumerated values variant"]
31 #[inline(always)]
32 pub const fn variant(&self) -> Option<Filtc1> {
33 match self.bits {
34 0 => Some(Filtc1::Interrupt),
35 1 => Some(Filtc1::DmaReq),
36 2 => Some(Filtc1::Trigger),
37 _ => None,
38 }
39 }
40 #[doc = "Interrupt"]
41 #[inline(always)]
42 pub fn is_interrupt(&self) -> bool {
43 *self == Filtc1::Interrupt
44 }
45 #[doc = "DMA request"]
46 #[inline(always)]
47 pub fn is_dma_req(&self) -> bool {
48 *self == Filtc1::DmaReq
49 }
50 #[doc = "Trigger event"]
51 #[inline(always)]
52 pub fn is_trigger(&self) -> bool {
53 *self == Filtc1::Trigger
54 }
55}
56#[doc = "Field `FILTC1` writer - Filter Configuration for FILTn"]
57pub type Filtc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filtc1>;
58impl<'a, REG> Filtc1W<'a, REG>
59where
60 REG: crate::Writable + crate::RegisterSpec,
61 REG::Ux: From<u8>,
62{
63 #[doc = "Interrupt"]
64 #[inline(always)]
65 pub fn interrupt(self) -> &'a mut crate::W<REG> {
66 self.variant(Filtc1::Interrupt)
67 }
68 #[doc = "DMA request"]
69 #[inline(always)]
70 pub fn dma_req(self) -> &'a mut crate::W<REG> {
71 self.variant(Filtc1::DmaReq)
72 }
73 #[doc = "Trigger event"]
74 #[inline(always)]
75 pub fn trigger(self) -> &'a mut crate::W<REG> {
76 self.variant(Filtc1::Trigger)
77 }
78}
79#[doc = "Filter Configuration for FILTn\n\nValue on reset: 0"]
80#[cfg_attr(feature = "defmt", derive(defmt::Format))]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82#[repr(u8)]
83pub enum Filtc2 {
84 #[doc = "0: Interrupt"]
85 Interrupt = 0,
86 #[doc = "1: DMA request"]
87 DmaReq = 1,
88 #[doc = "2: Trigger event"]
89 Trigger = 2,
90}
91impl From<Filtc2> for u8 {
92 #[inline(always)]
93 fn from(variant: Filtc2) -> Self {
94 variant as _
95 }
96}
97impl crate::FieldSpec for Filtc2 {
98 type Ux = u8;
99}
100impl crate::IsEnum for Filtc2 {}
101#[doc = "Field `FILTC2` reader - Filter Configuration for FILTn"]
102pub type Filtc2R = crate::FieldReader<Filtc2>;
103impl Filtc2R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub const fn variant(&self) -> Option<Filtc2> {
107 match self.bits {
108 0 => Some(Filtc2::Interrupt),
109 1 => Some(Filtc2::DmaReq),
110 2 => Some(Filtc2::Trigger),
111 _ => None,
112 }
113 }
114 #[doc = "Interrupt"]
115 #[inline(always)]
116 pub fn is_interrupt(&self) -> bool {
117 *self == Filtc2::Interrupt
118 }
119 #[doc = "DMA request"]
120 #[inline(always)]
121 pub fn is_dma_req(&self) -> bool {
122 *self == Filtc2::DmaReq
123 }
124 #[doc = "Trigger event"]
125 #[inline(always)]
126 pub fn is_trigger(&self) -> bool {
127 *self == Filtc2::Trigger
128 }
129}
130#[doc = "Field `FILTC2` writer - Filter Configuration for FILTn"]
131pub type Filtc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filtc2>;
132impl<'a, REG> Filtc2W<'a, REG>
133where
134 REG: crate::Writable + crate::RegisterSpec,
135 REG::Ux: From<u8>,
136{
137 #[doc = "Interrupt"]
138 #[inline(always)]
139 pub fn interrupt(self) -> &'a mut crate::W<REG> {
140 self.variant(Filtc2::Interrupt)
141 }
142 #[doc = "DMA request"]
143 #[inline(always)]
144 pub fn dma_req(self) -> &'a mut crate::W<REG> {
145 self.variant(Filtc2::DmaReq)
146 }
147 #[doc = "Trigger event"]
148 #[inline(always)]
149 pub fn trigger(self) -> &'a mut crate::W<REG> {
150 self.variant(Filtc2::Trigger)
151 }
152}
153impl R {
154 #[doc = "Bits 0:1 - Filter Configuration for FILTn"]
155 #[inline(always)]
156 pub fn filtc1(&self) -> Filtc1R {
157 Filtc1R::new((self.bits & 3) as u8)
158 }
159 #[doc = "Bits 2:3 - Filter Configuration for FILTn"]
160 #[inline(always)]
161 pub fn filtc2(&self) -> Filtc2R {
162 Filtc2R::new(((self.bits >> 2) & 3) as u8)
163 }
164}
165#[cfg(feature = "debug")]
166impl core::fmt::Debug for R {
167 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
168 f.debug_struct("FDC")
169 .field("filtc1", &self.filtc1())
170 .field("filtc2", &self.filtc2())
171 .finish()
172 }
173}
174impl W {
175 #[doc = "Bits 0:1 - Filter Configuration for FILTn"]
176 #[inline(always)]
177 pub fn filtc1(&mut self) -> Filtc1W<'_, FdcSpec> {
178 Filtc1W::new(self, 0)
179 }
180 #[doc = "Bits 2:3 - Filter Configuration for FILTn"]
181 #[inline(always)]
182 pub fn filtc2(&mut self) -> Filtc2W<'_, FdcSpec> {
183 Filtc2W::new(self, 2)
184 }
185}
186#[doc = "Pin Filter DMA/Trigger Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fdc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
187pub struct FdcSpec;
188impl crate::RegisterSpec for FdcSpec {
189 type Ux = u32;
190}
191#[doc = "`read()` method returns [`fdc::R`](R) reader structure"]
192impl crate::Readable for FdcSpec {}
193#[doc = "`write(|w| ..)` method takes [`fdc::W`](W) writer structure"]
194impl crate::Writable for FdcSpec {
195 type Safety = crate::Unsafe;
196}
197#[doc = "`reset()` method sets FDC to value 0"]
198impl crate::Resettable for FdcSpec {}