mcxa_pac/waketimer0/
wake_timer_ctrl.rs

1#[doc = "Register `WAKE_TIMER_CTRL` reader"]
2pub type R = crate::R<WakeTimerCtrlSpec>;
3#[doc = "Register `WAKE_TIMER_CTRL` writer"]
4pub type W = crate::W<WakeTimerCtrlSpec>;
5#[doc = "Wake Timer Status Flag\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum WakeFlag {
9    #[doc = "0: Wake timer has not timed out."]
10    Disable = 0,
11    #[doc = "1: Wake timer has timed out."]
12    Enable = 1,
13}
14impl From<WakeFlag> for bool {
15    #[inline(always)]
16    fn from(variant: WakeFlag) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `WAKE_FLAG` reader - Wake Timer Status Flag"]
21pub type WakeFlagR = crate::BitReader<WakeFlag>;
22impl WakeFlagR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> WakeFlag {
26        match self.bits {
27            false => WakeFlag::Disable,
28            true => WakeFlag::Enable,
29        }
30    }
31    #[doc = "Wake timer has not timed out."]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == WakeFlag::Disable
35    }
36    #[doc = "Wake timer has timed out."]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == WakeFlag::Enable
40    }
41}
42#[doc = "Field `WAKE_FLAG` writer - Wake Timer Status Flag"]
43pub type WakeFlagW<'a, REG> = crate::BitWriter1C<'a, REG, WakeFlag>;
44impl<'a, REG> WakeFlagW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Wake timer has not timed out."]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(WakeFlag::Disable)
52    }
53    #[doc = "Wake timer has timed out."]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(WakeFlag::Enable)
57    }
58}
59#[doc = "Clear Wake Timer\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ClrWakeTimer {
63    #[doc = "0: No effect."]
64    Disable = 0,
65    #[doc = "1: Clears the wake timer counter and halts operation until a new count value is loaded."]
66    Enable = 1,
67}
68impl From<ClrWakeTimer> for bool {
69    #[inline(always)]
70    fn from(variant: ClrWakeTimer) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `CLR_WAKE_TIMER` writer - Clear Wake Timer"]
75pub type ClrWakeTimerW<'a, REG> = crate::BitWriter<'a, REG, ClrWakeTimer>;
76impl<'a, REG> ClrWakeTimerW<'a, REG>
77where
78    REG: crate::Writable + crate::RegisterSpec,
79{
80    #[doc = "No effect."]
81    #[inline(always)]
82    pub fn disable(self) -> &'a mut crate::W<REG> {
83        self.variant(ClrWakeTimer::Disable)
84    }
85    #[doc = "Clears the wake timer counter and halts operation until a new count value is loaded."]
86    #[inline(always)]
87    pub fn enable(self) -> &'a mut crate::W<REG> {
88        self.variant(ClrWakeTimer::Enable)
89    }
90}
91#[doc = "OSC Divide Enable\n\nValue on reset: 0"]
92#[cfg_attr(feature = "defmt", derive(defmt::Format))]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94pub enum OscDivEna {
95    #[doc = "0: Disabled"]
96    Disable = 0,
97    #[doc = "1: Enabled"]
98    Enable = 1,
99}
100impl From<OscDivEna> for bool {
101    #[inline(always)]
102    fn from(variant: OscDivEna) -> Self {
103        variant as u8 != 0
104    }
105}
106#[doc = "Field `OSC_DIV_ENA` reader - OSC Divide Enable"]
107pub type OscDivEnaR = crate::BitReader<OscDivEna>;
108impl OscDivEnaR {
109    #[doc = "Get enumerated values variant"]
110    #[inline(always)]
111    pub const fn variant(&self) -> OscDivEna {
112        match self.bits {
113            false => OscDivEna::Disable,
114            true => OscDivEna::Enable,
115        }
116    }
117    #[doc = "Disabled"]
118    #[inline(always)]
119    pub fn is_disable(&self) -> bool {
120        *self == OscDivEna::Disable
121    }
122    #[doc = "Enabled"]
123    #[inline(always)]
124    pub fn is_enable(&self) -> bool {
125        *self == OscDivEna::Enable
126    }
127}
128#[doc = "Field `OSC_DIV_ENA` writer - OSC Divide Enable"]
129pub type OscDivEnaW<'a, REG> = crate::BitWriter<'a, REG, OscDivEna>;
130impl<'a, REG> OscDivEnaW<'a, REG>
131where
132    REG: crate::Writable + crate::RegisterSpec,
133{
134    #[doc = "Disabled"]
135    #[inline(always)]
136    pub fn disable(self) -> &'a mut crate::W<REG> {
137        self.variant(OscDivEna::Disable)
138    }
139    #[doc = "Enabled"]
140    #[inline(always)]
141    pub fn enable(self) -> &'a mut crate::W<REG> {
142        self.variant(OscDivEna::Enable)
143    }
144}
145#[doc = "Enable Interrupt\n\nValue on reset: 0"]
146#[cfg_attr(feature = "defmt", derive(defmt::Format))]
147#[derive(Clone, Copy, Debug, PartialEq, Eq)]
148pub enum IntrEn {
149    #[doc = "0: Disabled"]
150    Disable = 0,
151    #[doc = "1: Enabled"]
152    Enable = 1,
153}
154impl From<IntrEn> for bool {
155    #[inline(always)]
156    fn from(variant: IntrEn) -> Self {
157        variant as u8 != 0
158    }
159}
160#[doc = "Field `INTR_EN` reader - Enable Interrupt"]
161pub type IntrEnR = crate::BitReader<IntrEn>;
162impl IntrEnR {
163    #[doc = "Get enumerated values variant"]
164    #[inline(always)]
165    pub const fn variant(&self) -> IntrEn {
166        match self.bits {
167            false => IntrEn::Disable,
168            true => IntrEn::Enable,
169        }
170    }
171    #[doc = "Disabled"]
172    #[inline(always)]
173    pub fn is_disable(&self) -> bool {
174        *self == IntrEn::Disable
175    }
176    #[doc = "Enabled"]
177    #[inline(always)]
178    pub fn is_enable(&self) -> bool {
179        *self == IntrEn::Enable
180    }
181}
182#[doc = "Field `INTR_EN` writer - Enable Interrupt"]
183pub type IntrEnW<'a, REG> = crate::BitWriter<'a, REG, IntrEn>;
184impl<'a, REG> IntrEnW<'a, REG>
185where
186    REG: crate::Writable + crate::RegisterSpec,
187{
188    #[doc = "Disabled"]
189    #[inline(always)]
190    pub fn disable(self) -> &'a mut crate::W<REG> {
191        self.variant(IntrEn::Disable)
192    }
193    #[doc = "Enabled"]
194    #[inline(always)]
195    pub fn enable(self) -> &'a mut crate::W<REG> {
196        self.variant(IntrEn::Enable)
197    }
198}
199impl R {
200    #[doc = "Bit 1 - Wake Timer Status Flag"]
201    #[inline(always)]
202    pub fn wake_flag(&self) -> WakeFlagR {
203        WakeFlagR::new(((self.bits >> 1) & 1) != 0)
204    }
205    #[doc = "Bit 4 - OSC Divide Enable"]
206    #[inline(always)]
207    pub fn osc_div_ena(&self) -> OscDivEnaR {
208        OscDivEnaR::new(((self.bits >> 4) & 1) != 0)
209    }
210    #[doc = "Bit 5 - Enable Interrupt"]
211    #[inline(always)]
212    pub fn intr_en(&self) -> IntrEnR {
213        IntrEnR::new(((self.bits >> 5) & 1) != 0)
214    }
215}
216#[cfg(feature = "debug")]
217impl core::fmt::Debug for R {
218    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
219        f.debug_struct("WAKE_TIMER_CTRL")
220            .field("wake_flag", &self.wake_flag())
221            .field("osc_div_ena", &self.osc_div_ena())
222            .field("intr_en", &self.intr_en())
223            .finish()
224    }
225}
226impl W {
227    #[doc = "Bit 1 - Wake Timer Status Flag"]
228    #[inline(always)]
229    pub fn wake_flag(&mut self) -> WakeFlagW<'_, WakeTimerCtrlSpec> {
230        WakeFlagW::new(self, 1)
231    }
232    #[doc = "Bit 2 - Clear Wake Timer"]
233    #[inline(always)]
234    pub fn clr_wake_timer(&mut self) -> ClrWakeTimerW<'_, WakeTimerCtrlSpec> {
235        ClrWakeTimerW::new(self, 2)
236    }
237    #[doc = "Bit 4 - OSC Divide Enable"]
238    #[inline(always)]
239    pub fn osc_div_ena(&mut self) -> OscDivEnaW<'_, WakeTimerCtrlSpec> {
240        OscDivEnaW::new(self, 4)
241    }
242    #[doc = "Bit 5 - Enable Interrupt"]
243    #[inline(always)]
244    pub fn intr_en(&mut self) -> IntrEnW<'_, WakeTimerCtrlSpec> {
245        IntrEnW::new(self, 5)
246    }
247}
248#[doc = "Wake Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
249pub struct WakeTimerCtrlSpec;
250impl crate::RegisterSpec for WakeTimerCtrlSpec {
251    type Ux = u32;
252}
253#[doc = "`read()` method returns [`wake_timer_ctrl::R`](R) reader structure"]
254impl crate::Readable for WakeTimerCtrlSpec {}
255#[doc = "`write(|w| ..)` method takes [`wake_timer_ctrl::W`](W) writer structure"]
256impl crate::Writable for WakeTimerCtrlSpec {
257    type Safety = crate::Unsafe;
258    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x02;
259}
260#[doc = "`reset()` method sets WAKE_TIMER_CTRL to value 0"]
261impl crate::Resettable for WakeTimerCtrlSpec {}
mcxa_pac/waketimer0/wake_timer_ctrl.rs

mcxa_pac/waketimer0/
wake_timer_ctrl.rs
