mcxa_pac/usb0/
otgistat.rs

1#[doc = "Register `OTGISTAT` reader"]
2pub type R = crate::R<OtgistatSpec>;
3#[doc = "Register `OTGISTAT` writer"]
4pub type W = crate::W<OtgistatSpec>;
5#[doc = "Line State Change Interrupt Flag\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum LineStateChg {
9    #[doc = "0: Interrupt did not occur"]
10    IntNo = 0,
11    #[doc = "1: Interrupt occurred"]
12    IntYes = 1,
13}
14impl From<LineStateChg> for bool {
15    #[inline(always)]
16    fn from(variant: LineStateChg) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `LINE_STATE_CHG` reader - Line State Change Interrupt Flag"]
21pub type LineStateChgR = crate::BitReader<LineStateChg>;
22impl LineStateChgR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> LineStateChg {
26        match self.bits {
27            false => LineStateChg::IntNo,
28            true => LineStateChg::IntYes,
29        }
30    }
31    #[doc = "Interrupt did not occur"]
32    #[inline(always)]
33    pub fn is_int_no(&self) -> bool {
34        *self == LineStateChg::IntNo
35    }
36    #[doc = "Interrupt occurred"]
37    #[inline(always)]
38    pub fn is_int_yes(&self) -> bool {
39        *self == LineStateChg::IntYes
40    }
41}
42#[doc = "Field `LINE_STATE_CHG` writer - Line State Change Interrupt Flag"]
43pub type LineStateChgW<'a, REG> = crate::BitWriter1C<'a, REG, LineStateChg>;
44impl<'a, REG> LineStateChgW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Interrupt did not occur"]
49    #[inline(always)]
50    pub fn int_no(self) -> &'a mut crate::W<REG> {
51        self.variant(LineStateChg::IntNo)
52    }
53    #[doc = "Interrupt occurred"]
54    #[inline(always)]
55    pub fn int_yes(self) -> &'a mut crate::W<REG> {
56        self.variant(LineStateChg::IntYes)
57    }
58}
59#[doc = "One Millisecond Timer Timeout Flag\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Onemsec {
63    #[doc = "0: Not timed out"]
64    IntNo = 0,
65    #[doc = "1: Timed out"]
66    IntYes = 1,
67}
68impl From<Onemsec> for bool {
69    #[inline(always)]
70    fn from(variant: Onemsec) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `ONEMSEC` reader - One Millisecond Timer Timeout Flag"]
75pub type OnemsecR = crate::BitReader<Onemsec>;
76impl OnemsecR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Onemsec {
80        match self.bits {
81            false => Onemsec::IntNo,
82            true => Onemsec::IntYes,
83        }
84    }
85    #[doc = "Not timed out"]
86    #[inline(always)]
87    pub fn is_int_no(&self) -> bool {
88        *self == Onemsec::IntNo
89    }
90    #[doc = "Timed out"]
91    #[inline(always)]
92    pub fn is_int_yes(&self) -> bool {
93        *self == Onemsec::IntYes
94    }
95}
96#[doc = "Field `ONEMSEC` writer - One Millisecond Timer Timeout Flag"]
97pub type OnemsecW<'a, REG> = crate::BitWriter1C<'a, REG, Onemsec>;
98impl<'a, REG> OnemsecW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Not timed out"]
103    #[inline(always)]
104    pub fn int_no(self) -> &'a mut crate::W<REG> {
105        self.variant(Onemsec::IntNo)
106    }
107    #[doc = "Timed out"]
108    #[inline(always)]
109    pub fn int_yes(self) -> &'a mut crate::W<REG> {
110        self.variant(Onemsec::IntYes)
111    }
112}
113impl R {
114    #[doc = "Bit 5 - Line State Change Interrupt Flag"]
115    #[inline(always)]
116    pub fn line_state_chg(&self) -> LineStateChgR {
117        LineStateChgR::new(((self.bits >> 5) & 1) != 0)
118    }
119    #[doc = "Bit 6 - One Millisecond Timer Timeout Flag"]
120    #[inline(always)]
121    pub fn onemsec(&self) -> OnemsecR {
122        OnemsecR::new(((self.bits >> 6) & 1) != 0)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("OTGISTAT")
129            .field("line_state_chg", &self.line_state_chg())
130            .field("onemsec", &self.onemsec())
131            .finish()
132    }
133}
134impl W {
135    #[doc = "Bit 5 - Line State Change Interrupt Flag"]
136    #[inline(always)]
137    pub fn line_state_chg(&mut self) -> LineStateChgW<'_, OtgistatSpec> {
138        LineStateChgW::new(self, 5)
139    }
140    #[doc = "Bit 6 - One Millisecond Timer Timeout Flag"]
141    #[inline(always)]
142    pub fn onemsec(&mut self) -> OnemsecW<'_, OtgistatSpec> {
143        OnemsecW::new(self, 6)
144    }
145}
146#[doc = "OTG Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgistat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgistat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
147pub struct OtgistatSpec;
148impl crate::RegisterSpec for OtgistatSpec {
149    type Ux = u8;
150}
151#[doc = "`read()` method returns [`otgistat::R`](R) reader structure"]
152impl crate::Readable for OtgistatSpec {}
153#[doc = "`write(|w| ..)` method takes [`otgistat::W`](W) writer structure"]
154impl crate::Writable for OtgistatSpec {
155    type Safety = crate::Unsafe;
156    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0x60;
157}
158#[doc = "`reset()` method sets OTGISTAT to value 0"]
159impl crate::Resettable for OtgistatSpec {}
mcxa_pac/usb0/otgistat.rs

mcxa_pac/usb0/
otgistat.rs
