mcxa_pac/trng0/
sdctl.rs

1#[doc = "Register `SDCTL` reader"]
2pub type R = crate::R<SdctlSpec>;
3#[doc = "Register `SDCTL` writer"]
4pub type W = crate::W<SdctlSpec>;
5#[doc = "Field `SAMP_SIZE` reader - Sample Size"]
6pub type SampSizeR = crate::FieldReader<u16>;
7#[doc = "Field `SAMP_SIZE` writer - Sample Size"]
8pub type SampSizeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `ENT_DLY` reader - Entropy Delay"]
10pub type EntDlyR = crate::FieldReader<u16>;
11#[doc = "Field `ENT_DLY` writer - Entropy Delay"]
12pub type EntDlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - Sample Size"]
15    #[inline(always)]
16    pub fn samp_size(&self) -> SampSizeR {
17        SampSizeR::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - Entropy Delay"]
20    #[inline(always)]
21    pub fn ent_dly(&self) -> EntDlyR {
22        EntDlyR::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25#[cfg(feature = "debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("SDCTL")
29            .field("samp_size", &self.samp_size())
30            .field("ent_dly", &self.ent_dly())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - Sample Size"]
36    #[inline(always)]
37    pub fn samp_size(&mut self) -> SampSizeW<'_, SdctlSpec> {
38        SampSizeW::new(self, 0)
39    }
40    #[doc = "Bits 16:31 - Entropy Delay"]
41    #[inline(always)]
42    pub fn ent_dly(&mut self) -> EntDlyW<'_, SdctlSpec> {
43        EntDlyW::new(self, 16)
44    }
45}
46#[doc = "Seed Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct SdctlSpec;
48impl crate::RegisterSpec for SdctlSpec {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`sdctl::R`](R) reader structure"]
52impl crate::Readable for SdctlSpec {}
53#[doc = "`write(|w| ..)` method takes [`sdctl::W`](W) writer structure"]
54impl crate::Writable for SdctlSpec {
55    type Safety = crate::Unsafe;
56}
57#[doc = "`reset()` method sets SDCTL to value 0x0c80_0200"]
58impl crate::Resettable for SdctlSpec {
59    const RESET_VALUE: u32 = 0x0c80_0200;
60}
mcxa_pac/trng0/sdctl.rs

mcxa_pac/trng0/
sdctl.rs
