mcxa_pac/trng0/
mctl.rs

1#[doc = "Register `MCTL` reader"]
2pub type R = crate::R<MctlSpec>;
3#[doc = "Register `MCTL` writer"]
4pub type W = crate::W<MctlSpec>;
5#[doc = "Oscillator1 Divide\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum OscDiv {
10    #[doc = "0: use ring oscillator with no divide"]
11    OscDivDiv1 = 0,
12    #[doc = "1: use ring oscillator divided-by-2"]
13    OscDivDiv2 = 1,
14    #[doc = "2: use ring oscillator divided-by-4"]
15    OscDivDiv4 = 2,
16    #[doc = "3: use ring oscillator divided-by-8"]
17    OscDivDiv8 = 3,
18}
19impl From<OscDiv> for u8 {
20    #[inline(always)]
21    fn from(variant: OscDiv) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for OscDiv {
26    type Ux = u8;
27}
28impl crate::IsEnum for OscDiv {}
29#[doc = "Field `OSC_DIV` reader - Oscillator1 Divide"]
30pub type OscDivR = crate::FieldReader<OscDiv>;
31impl OscDivR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> OscDiv {
35        match self.bits {
36            0 => OscDiv::OscDivDiv1,
37            1 => OscDiv::OscDivDiv2,
38            2 => OscDiv::OscDivDiv4,
39            3 => OscDiv::OscDivDiv8,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "use ring oscillator with no divide"]
44    #[inline(always)]
45    pub fn is_osc_div_div1(&self) -> bool {
46        *self == OscDiv::OscDivDiv1
47    }
48    #[doc = "use ring oscillator divided-by-2"]
49    #[inline(always)]
50    pub fn is_osc_div_div2(&self) -> bool {
51        *self == OscDiv::OscDivDiv2
52    }
53    #[doc = "use ring oscillator divided-by-4"]
54    #[inline(always)]
55    pub fn is_osc_div_div4(&self) -> bool {
56        *self == OscDiv::OscDivDiv4
57    }
58    #[doc = "use ring oscillator divided-by-8"]
59    #[inline(always)]
60    pub fn is_osc_div_div8(&self) -> bool {
61        *self == OscDiv::OscDivDiv8
62    }
63}
64#[doc = "Field `OSC_DIV` writer - Oscillator1 Divide"]
65pub type OscDivW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscDiv, crate::Safe>;
66impl<'a, REG> OscDivW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "use ring oscillator with no divide"]
72    #[inline(always)]
73    pub fn osc_div_div1(self) -> &'a mut crate::W<REG> {
74        self.variant(OscDiv::OscDivDiv1)
75    }
76    #[doc = "use ring oscillator divided-by-2"]
77    #[inline(always)]
78    pub fn osc_div_div2(self) -> &'a mut crate::W<REG> {
79        self.variant(OscDiv::OscDivDiv2)
80    }
81    #[doc = "use ring oscillator divided-by-4"]
82    #[inline(always)]
83    pub fn osc_div_div4(self) -> &'a mut crate::W<REG> {
84        self.variant(OscDiv::OscDivDiv4)
85    }
86    #[doc = "use ring oscillator divided-by-8"]
87    #[inline(always)]
88    pub fn osc_div_div8(self) -> &'a mut crate::W<REG> {
89        self.variant(OscDiv::OscDivDiv8)
90    }
91}
92#[doc = "Field `DIS_SLF_TST` writer - Disable Self-Tests"]
93pub type DisSlfTstW<'a, REG> = crate::BitWriter<'a, REG>;
94#[doc = "Field `TRNG_ACC` reader - TRNG Access Mode"]
95pub type TrngAccR = crate::BitReader;
96#[doc = "Field `TRNG_ACC` writer - TRNG Access Mode"]
97pub type TrngAccW<'a, REG> = crate::BitWriter<'a, REG>;
98#[doc = "Reset Defaults\n\nValue on reset: 0"]
99#[cfg_attr(feature = "defmt", derive(defmt::Format))]
100#[derive(Clone, Copy, Debug, PartialEq, Eq)]
101pub enum RstDef {
102    #[doc = "0: No impact."]
103    Disable = 0,
104    #[doc = "1: Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state."]
105    Enable = 1,
106}
107impl From<RstDef> for bool {
108    #[inline(always)]
109    fn from(variant: RstDef) -> Self {
110        variant as u8 != 0
111    }
112}
113#[doc = "Field `RST_DEF` writer - Reset Defaults"]
114pub type RstDefW<'a, REG> = crate::BitWriter<'a, REG, RstDef>;
115impl<'a, REG> RstDefW<'a, REG>
116where
117    REG: crate::Writable + crate::RegisterSpec,
118{
119    #[doc = "No impact."]
120    #[inline(always)]
121    pub fn disable(self) -> &'a mut crate::W<REG> {
122        self.variant(RstDef::Disable)
123    }
124    #[doc = "Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state."]
125    #[inline(always)]
126    pub fn enable(self) -> &'a mut crate::W<REG> {
127        self.variant(RstDef::Enable)
128    }
129}
130#[doc = "Field `FCT_FAIL` reader - Frequency Count Fail"]
131pub type FctFailR = crate::BitReader;
132#[doc = "Frequency Count Valid\n\nValue on reset: 0"]
133#[cfg_attr(feature = "defmt", derive(defmt::Format))]
134#[derive(Clone, Copy, Debug, PartialEq, Eq)]
135pub enum FctVal {
136    #[doc = "0: Frequency Count is not valid"]
137    Disable = 0,
138    #[doc = "1: Frequency Count is valid"]
139    Enable = 1,
140}
141impl From<FctVal> for bool {
142    #[inline(always)]
143    fn from(variant: FctVal) -> Self {
144        variant as u8 != 0
145    }
146}
147#[doc = "Field `FCT_VAL` reader - Frequency Count Valid"]
148pub type FctValR = crate::BitReader<FctVal>;
149impl FctValR {
150    #[doc = "Get enumerated values variant"]
151    #[inline(always)]
152    pub const fn variant(&self) -> FctVal {
153        match self.bits {
154            false => FctVal::Disable,
155            true => FctVal::Enable,
156        }
157    }
158    #[doc = "Frequency Count is not valid"]
159    #[inline(always)]
160    pub fn is_disable(&self) -> bool {
161        *self == FctVal::Disable
162    }
163    #[doc = "Frequency Count is valid"]
164    #[inline(always)]
165    pub fn is_enable(&self) -> bool {
166        *self == FctVal::Enable
167    }
168}
169#[doc = "Entropy Valid\n\nValue on reset: 0"]
170#[cfg_attr(feature = "defmt", derive(defmt::Format))]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172pub enum EntVal {
173    #[doc = "0: Entropy is not valid"]
174    Disable = 0,
175    #[doc = "1: Entropy is valid"]
176    Enable = 1,
177}
178impl From<EntVal> for bool {
179    #[inline(always)]
180    fn from(variant: EntVal) -> Self {
181        variant as u8 != 0
182    }
183}
184#[doc = "Field `ENT_VAL` reader - Entropy Valid"]
185pub type EntValR = crate::BitReader<EntVal>;
186impl EntValR {
187    #[doc = "Get enumerated values variant"]
188    #[inline(always)]
189    pub const fn variant(&self) -> EntVal {
190        match self.bits {
191            false => EntVal::Disable,
192            true => EntVal::Enable,
193        }
194    }
195    #[doc = "Entropy is not valid"]
196    #[inline(always)]
197    pub fn is_disable(&self) -> bool {
198        *self == EntVal::Disable
199    }
200    #[doc = "Entropy is valid"]
201    #[inline(always)]
202    pub fn is_enable(&self) -> bool {
203        *self == EntVal::Enable
204    }
205}
206#[doc = "Error Status\n\nValue on reset: 0"]
207#[cfg_attr(feature = "defmt", derive(defmt::Format))]
208#[derive(Clone, Copy, Debug, PartialEq, Eq)]
209pub enum Err {
210    #[doc = "0: No error"]
211    Disable = 0,
212    #[doc = "1: Error detected"]
213    Enable = 1,
214}
215impl From<Err> for bool {
216    #[inline(always)]
217    fn from(variant: Err) -> Self {
218        variant as u8 != 0
219    }
220}
221#[doc = "Field `ERR` reader - Error Status"]
222pub type ErrR = crate::BitReader<Err>;
223impl ErrR {
224    #[doc = "Get enumerated values variant"]
225    #[inline(always)]
226    pub const fn variant(&self) -> Err {
227        match self.bits {
228            false => Err::Disable,
229            true => Err::Enable,
230        }
231    }
232    #[doc = "No error"]
233    #[inline(always)]
234    pub fn is_disable(&self) -> bool {
235        *self == Err::Disable
236    }
237    #[doc = "Error detected"]
238    #[inline(always)]
239    pub fn is_enable(&self) -> bool {
240        *self == Err::Enable
241    }
242}
243#[doc = "Field `ERR` writer - Error Status"]
244pub type ErrW<'a, REG> = crate::BitWriter1C<'a, REG, Err>;
245impl<'a, REG> ErrW<'a, REG>
246where
247    REG: crate::Writable + crate::RegisterSpec,
248{
249    #[doc = "No error"]
250    #[inline(always)]
251    pub fn disable(self) -> &'a mut crate::W<REG> {
252        self.variant(Err::Disable)
253    }
254    #[doc = "Error detected"]
255    #[inline(always)]
256    pub fn enable(self) -> &'a mut crate::W<REG> {
257        self.variant(Err::Enable)
258    }
259}
260#[doc = "TRNG is ok to stop\n\nValue on reset: 1"]
261#[cfg_attr(feature = "defmt", derive(defmt::Format))]
262#[derive(Clone, Copy, Debug, PartialEq, Eq)]
263pub enum TstopOk {
264    #[doc = "0: TRNG is generating entropy and is not ok to stop"]
265    Disable = 0,
266    #[doc = "1: TRNG is not generating entropy and is ok to stop"]
267    Enable = 1,
268}
269impl From<TstopOk> for bool {
270    #[inline(always)]
271    fn from(variant: TstopOk) -> Self {
272        variant as u8 != 0
273    }
274}
275#[doc = "Field `TSTOP_OK` reader - TRNG is ok to stop"]
276pub type TstopOkR = crate::BitReader<TstopOk>;
277impl TstopOkR {
278    #[doc = "Get enumerated values variant"]
279    #[inline(always)]
280    pub const fn variant(&self) -> TstopOk {
281        match self.bits {
282            false => TstopOk::Disable,
283            true => TstopOk::Enable,
284        }
285    }
286    #[doc = "TRNG is generating entropy and is not ok to stop"]
287    #[inline(always)]
288    pub fn is_disable(&self) -> bool {
289        *self == TstopOk::Disable
290    }
291    #[doc = "TRNG is not generating entropy and is ok to stop"]
292    #[inline(always)]
293    pub fn is_enable(&self) -> bool {
294        *self == TstopOk::Enable
295    }
296}
297#[doc = "Oscillator 2 Failure\n\nValue on reset: 0"]
298#[cfg_attr(feature = "defmt", derive(defmt::Format))]
299#[derive(Clone, Copy, Debug, PartialEq, Eq)]
300pub enum Osc2Fail {
301    #[doc = "0: Oscillator 2 is running."]
302    Disable = 0,
303    #[doc = "1: Oscillator 2 has failed (see OSC2_CTL\\[OSC_FAILSAFE_LMT\\])."]
304    Enable = 1,
305}
306impl From<Osc2Fail> for bool {
307    #[inline(always)]
308    fn from(variant: Osc2Fail) -> Self {
309        variant as u8 != 0
310    }
311}
312#[doc = "Field `OSC2_FAIL` reader - Oscillator 2 Failure"]
313pub type Osc2FailR = crate::BitReader<Osc2Fail>;
314impl Osc2FailR {
315    #[doc = "Get enumerated values variant"]
316    #[inline(always)]
317    pub const fn variant(&self) -> Osc2Fail {
318        match self.bits {
319            false => Osc2Fail::Disable,
320            true => Osc2Fail::Enable,
321        }
322    }
323    #[doc = "Oscillator 2 is running."]
324    #[inline(always)]
325    pub fn is_disable(&self) -> bool {
326        *self == Osc2Fail::Disable
327    }
328    #[doc = "Oscillator 2 has failed (see OSC2_CTL\\[OSC_FAILSAFE_LMT\\])."]
329    #[inline(always)]
330    pub fn is_enable(&self) -> bool {
331        *self == Osc2Fail::Enable
332    }
333}
334#[doc = "Program Mode\n\nValue on reset: 1"]
335#[cfg_attr(feature = "defmt", derive(defmt::Format))]
336#[derive(Clone, Copy, Debug, PartialEq, Eq)]
337pub enum Prgm {
338    #[doc = "0: TRNG is in Run Mode"]
339    Disable = 0,
340    #[doc = "1: TRNG is in Program Mode"]
341    Enable = 1,
342}
343impl From<Prgm> for bool {
344    #[inline(always)]
345    fn from(variant: Prgm) -> Self {
346        variant as u8 != 0
347    }
348}
349#[doc = "Field `PRGM` reader - Program Mode"]
350pub type PrgmR = crate::BitReader<Prgm>;
351impl PrgmR {
352    #[doc = "Get enumerated values variant"]
353    #[inline(always)]
354    pub const fn variant(&self) -> Prgm {
355        match self.bits {
356            false => Prgm::Disable,
357            true => Prgm::Enable,
358        }
359    }
360    #[doc = "TRNG is in Run Mode"]
361    #[inline(always)]
362    pub fn is_disable(&self) -> bool {
363        *self == Prgm::Disable
364    }
365    #[doc = "TRNG is in Program Mode"]
366    #[inline(always)]
367    pub fn is_enable(&self) -> bool {
368        *self == Prgm::Enable
369    }
370}
371#[doc = "Field `PRGM` writer - Program Mode"]
372pub type PrgmW<'a, REG> = crate::BitWriter<'a, REG, Prgm>;
373impl<'a, REG> PrgmW<'a, REG>
374where
375    REG: crate::Writable + crate::RegisterSpec,
376{
377    #[doc = "TRNG is in Run Mode"]
378    #[inline(always)]
379    pub fn disable(self) -> &'a mut crate::W<REG> {
380        self.variant(Prgm::Disable)
381    }
382    #[doc = "TRNG is in Program Mode"]
383    #[inline(always)]
384    pub fn enable(self) -> &'a mut crate::W<REG> {
385        self.variant(Prgm::Enable)
386    }
387}
388#[doc = "Integrity Error\n\nValue on reset: 0"]
389#[cfg_attr(feature = "defmt", derive(defmt::Format))]
390#[derive(Clone, Copy, Debug, PartialEq, Eq)]
391pub enum IntgErr {
392    #[doc = "0: TRNG detected no internal bit error"]
393    Disable = 0,
394    #[doc = "1: TRNG detected internal bit error(s)"]
395    Enable = 1,
396}
397impl From<IntgErr> for bool {
398    #[inline(always)]
399    fn from(variant: IntgErr) -> Self {
400        variant as u8 != 0
401    }
402}
403#[doc = "Field `INTG_ERR` reader - Integrity Error"]
404pub type IntgErrR = crate::BitReader<IntgErr>;
405impl IntgErrR {
406    #[doc = "Get enumerated values variant"]
407    #[inline(always)]
408    pub const fn variant(&self) -> IntgErr {
409        match self.bits {
410            false => IntgErr::Disable,
411            true => IntgErr::Enable,
412        }
413    }
414    #[doc = "TRNG detected no internal bit error"]
415    #[inline(always)]
416    pub fn is_disable(&self) -> bool {
417        *self == IntgErr::Disable
418    }
419    #[doc = "TRNG detected internal bit error(s)"]
420    #[inline(always)]
421    pub fn is_enable(&self) -> bool {
422        *self == IntgErr::Enable
423    }
424}
425impl R {
426    #[doc = "Bits 2:3 - Oscillator1 Divide"]
427    #[inline(always)]
428    pub fn osc_div(&self) -> OscDivR {
429        OscDivR::new(((self.bits >> 2) & 3) as u8)
430    }
431    #[doc = "Bit 5 - TRNG Access Mode"]
432    #[inline(always)]
433    pub fn trng_acc(&self) -> TrngAccR {
434        TrngAccR::new(((self.bits >> 5) & 1) != 0)
435    }
436    #[doc = "Bit 8 - Frequency Count Fail"]
437    #[inline(always)]
438    pub fn fct_fail(&self) -> FctFailR {
439        FctFailR::new(((self.bits >> 8) & 1) != 0)
440    }
441    #[doc = "Bit 9 - Frequency Count Valid"]
442    #[inline(always)]
443    pub fn fct_val(&self) -> FctValR {
444        FctValR::new(((self.bits >> 9) & 1) != 0)
445    }
446    #[doc = "Bit 10 - Entropy Valid"]
447    #[inline(always)]
448    pub fn ent_val(&self) -> EntValR {
449        EntValR::new(((self.bits >> 10) & 1) != 0)
450    }
451    #[doc = "Bit 12 - Error Status"]
452    #[inline(always)]
453    pub fn err(&self) -> ErrR {
454        ErrR::new(((self.bits >> 12) & 1) != 0)
455    }
456    #[doc = "Bit 13 - TRNG is ok to stop"]
457    #[inline(always)]
458    pub fn tstop_ok(&self) -> TstopOkR {
459        TstopOkR::new(((self.bits >> 13) & 1) != 0)
460    }
461    #[doc = "Bit 15 - Oscillator 2 Failure"]
462    #[inline(always)]
463    pub fn osc2_fail(&self) -> Osc2FailR {
464        Osc2FailR::new(((self.bits >> 15) & 1) != 0)
465    }
466    #[doc = "Bit 16 - Program Mode"]
467    #[inline(always)]
468    pub fn prgm(&self) -> PrgmR {
469        PrgmR::new(((self.bits >> 16) & 1) != 0)
470    }
471    #[doc = "Bit 31 - Integrity Error"]
472    #[inline(always)]
473    pub fn intg_err(&self) -> IntgErrR {
474        IntgErrR::new(((self.bits >> 31) & 1) != 0)
475    }
476}
477#[cfg(feature = "debug")]
478impl core::fmt::Debug for R {
479    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
480        f.debug_struct("MCTL")
481            .field("osc_div", &self.osc_div())
482            .field("trng_acc", &self.trng_acc())
483            .field("fct_fail", &self.fct_fail())
484            .field("fct_val", &self.fct_val())
485            .field("ent_val", &self.ent_val())
486            .field("err", &self.err())
487            .field("tstop_ok", &self.tstop_ok())
488            .field("osc2_fail", &self.osc2_fail())
489            .field("prgm", &self.prgm())
490            .field("intg_err", &self.intg_err())
491            .finish()
492    }
493}
494impl W {
495    #[doc = "Bits 2:3 - Oscillator1 Divide"]
496    #[inline(always)]
497    pub fn osc_div(&mut self) -> OscDivW<'_, MctlSpec> {
498        OscDivW::new(self, 2)
499    }
500    #[doc = "Bit 4 - Disable Self-Tests"]
501    #[inline(always)]
502    pub fn dis_slf_tst(&mut self) -> DisSlfTstW<'_, MctlSpec> {
503        DisSlfTstW::new(self, 4)
504    }
505    #[doc = "Bit 5 - TRNG Access Mode"]
506    #[inline(always)]
507    pub fn trng_acc(&mut self) -> TrngAccW<'_, MctlSpec> {
508        TrngAccW::new(self, 5)
509    }
510    #[doc = "Bit 6 - Reset Defaults"]
511    #[inline(always)]
512    pub fn rst_def(&mut self) -> RstDefW<'_, MctlSpec> {
513        RstDefW::new(self, 6)
514    }
515    #[doc = "Bit 12 - Error Status"]
516    #[inline(always)]
517    pub fn err(&mut self) -> ErrW<'_, MctlSpec> {
518        ErrW::new(self, 12)
519    }
520    #[doc = "Bit 16 - Program Mode"]
521    #[inline(always)]
522    pub fn prgm(&mut self) -> PrgmW<'_, MctlSpec> {
523        PrgmW::new(self, 16)
524    }
525}
526#[doc = "Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
527pub struct MctlSpec;
528impl crate::RegisterSpec for MctlSpec {
529    type Ux = u32;
530}
531#[doc = "`read()` method returns [`mctl::R`](R) reader structure"]
532impl crate::Readable for MctlSpec {}
533#[doc = "`write(|w| ..)` method takes [`mctl::W`](W) writer structure"]
534impl crate::Writable for MctlSpec {
535    type Safety = crate::Unsafe;
536    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1000;
537}
538#[doc = "`reset()` method sets MCTL to value 0x0001_2000"]
539impl crate::Resettable for MctlSpec {
540    const RESET_VALUE: u32 = 0x0001_2000;
541}
mcxa_pac/trng0/mctl.rs

mcxa_pac/trng0/
mctl.rs
