1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 mctl: Mctl,
6 scmisc: Scmisc,
7 pkrrng: Pkrrng,
8 _reserved_3_pkrsq: [u8; 0x04],
9 sdctl: Sdctl,
10 _reserved_5_sblim: [u8; 0x04],
11 _reserved_6_frqmin: [u8; 0x04],
12 _reserved_7_frqcnt: [u8; 0x04],
13 _reserved_8_scmc: [u8; 0x04],
14 _reserved_9_scr: [u8; 0x04],
15 _reserved_10_scr: [u8; 0x04],
16 _reserved_11_scr: [u8; 0x04],
17 _reserved_12_scr: [u8; 0x04],
18 _reserved_13_scr: [u8; 0x04],
19 _reserved_14_scr: [u8; 0x04],
20 status: Status,
21 ent: [Ent; 8],
22 _reserved17: [u8; 0x20],
23 pkrcnt10: Pkrcnt10,
24 pkrcnt32: Pkrcnt32,
25 pkrcnt54: Pkrcnt54,
26 pkrcnt76: Pkrcnt76,
27 pkrcnt98: Pkrcnt98,
28 pkrcntba: Pkrcntba,
29 pkrcntdc: Pkrcntdc,
30 pkrcntfe: Pkrcntfe,
31 sec_cfg: SecCfg,
32 int_ctrl: IntCtrl,
33 int_mask: IntMask,
34 int_status: IntStatus,
35 cser: Cser,
36 csclr: Csclr,
37 _reserved31: [u8; 0x34],
38 osc2_ctl: Osc2Ctl,
39 vid1: Vid1,
40 vid2: Vid2,
41}
42impl RegisterBlock {
43 #[doc = "0x00 - Miscellaneous Control Register"]
44 #[inline(always)]
45 pub const fn mctl(&self) -> &Mctl {
46 &self.mctl
47 }
48 #[doc = "0x04 - Statistical Check Miscellaneous Register"]
49 #[inline(always)]
50 pub const fn scmisc(&self) -> &Scmisc {
51 &self.scmisc
52 }
53 #[doc = "0x08 - Poker Range Register"]
54 #[inline(always)]
55 pub const fn pkrrng(&self) -> &Pkrrng {
56 &self.pkrrng
57 }
58 #[doc = "0x0c - Poker Square Calculation Result Register"]
59 #[inline(always)]
60 pub const fn pkrsq(&self) -> &Pkrsq {
61 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
62 }
63 #[doc = "0x0c - Poker Maximum Limit Register"]
64 #[inline(always)]
65 pub const fn pkrmax(&self) -> &Pkrmax {
66 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
67 }
68 #[doc = "0x10 - Seed Control Register"]
69 #[inline(always)]
70 pub const fn sdctl(&self) -> &Sdctl {
71 &self.sdctl
72 }
73 #[doc = "0x14 - Total Samples Register"]
74 #[inline(always)]
75 pub const fn totsam(&self) -> &Totsam {
76 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
77 }
78 #[doc = "0x14 - Sparse Bit Limit Register"]
79 #[inline(always)]
80 pub const fn sblim(&self) -> &Sblim {
81 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
82 }
83 #[doc = "0x18 - Oscillator-2 Frequency Count Register"]
84 #[inline(always)]
85 pub const fn osc2_frqcnt(&self) -> &Osc2Frqcnt {
86 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
87 }
88 #[doc = "0x18 - Frequency Count Minimum Limit Register"]
89 #[inline(always)]
90 pub const fn frqmin(&self) -> &Frqmin {
91 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
92 }
93 #[doc = "0x1c - Frequency Count Maximum Limit Register"]
94 #[inline(always)]
95 pub const fn frqmax(&self) -> &Frqmax {
96 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
97 }
98 #[doc = "0x1c - Frequency Count Register"]
99 #[inline(always)]
100 pub const fn frqcnt(&self) -> &Frqcnt {
101 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
102 }
103 #[doc = "0x20 - Statistical Check Monobit Limit Register"]
104 #[inline(always)]
105 pub const fn scml(&self) -> &Scml {
106 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
107 }
108 #[doc = "0x20 - Statistical Check Monobit Count Register"]
109 #[inline(always)]
110 pub const fn scmc(&self) -> &Scmc {
111 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
112 }
113 #[doc = "0x24 - Statistical Check Run Length 1 Limit Register"]
114 #[inline(always)]
115 pub const fn scr1l(&self) -> &Scr1l {
116 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
117 }
118 #[doc = "0x24 - Statistical Check Run Length 1 Count Register"]
119 #[inline(always)]
120 pub const fn scr1c(&self) -> &Scr1c {
121 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
122 }
123 #[doc = "0x28 - Statistical Check Run Length 2 Limit Register"]
124 #[inline(always)]
125 pub const fn scr2l(&self) -> &Scr2l {
126 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
127 }
128 #[doc = "0x28 - Statistical Check Run Length 2 Count Register"]
129 #[inline(always)]
130 pub const fn scr2c(&self) -> &Scr2c {
131 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
132 }
133 #[doc = "0x2c - Statistical Check Run Length 3 Limit Register"]
134 #[inline(always)]
135 pub const fn scr3l(&self) -> &Scr3l {
136 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
137 }
138 #[doc = "0x2c - Statistical Check Run Length 3 Count Register"]
139 #[inline(always)]
140 pub const fn scr3c(&self) -> &Scr3c {
141 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
142 }
143 #[doc = "0x30 - Statistical Check Run Length 4 Limit Register"]
144 #[inline(always)]
145 pub const fn scr4l(&self) -> &Scr4l {
146 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).cast() }
147 }
148 #[doc = "0x30 - Statistical Check Run Length 4 Count Register"]
149 #[inline(always)]
150 pub const fn scr4c(&self) -> &Scr4c {
151 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).cast() }
152 }
153 #[doc = "0x34 - Statistical Check Run Length 5 Limit Register"]
154 #[inline(always)]
155 pub const fn scr5l(&self) -> &Scr5l {
156 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(52).cast() }
157 }
158 #[doc = "0x34 - Statistical Check Run Length 5 Count Register"]
159 #[inline(always)]
160 pub const fn scr5c(&self) -> &Scr5c {
161 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(52).cast() }
162 }
163 #[doc = "0x38 - Statistical Check Run Length 6+ Limit Register"]
164 #[inline(always)]
165 pub const fn scr6pl(&self) -> &Scr6pl {
166 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(56).cast() }
167 }
168 #[doc = "0x38 - Statistical Check Run Length 6+ Count Register"]
169 #[inline(always)]
170 pub const fn scr6pc(&self) -> &Scr6pc {
171 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(56).cast() }
172 }
173 #[doc = "0x3c - Status Register"]
174 #[inline(always)]
175 pub const fn status(&self) -> &Status {
176 &self.status
177 }
178 #[doc = "0x40..0x60 - Entropy Read Register"]
179 #[inline(always)]
180 pub const fn ent(&self, n: usize) -> &Ent {
181 &self.ent[n]
182 }
183 #[doc = "Iterator for array of:"]
184 #[doc = "0x40..0x60 - Entropy Read Register"]
185 #[inline(always)]
186 pub fn ent_iter(&self) -> impl Iterator<Item = &Ent> {
187 self.ent.iter()
188 }
189 #[doc = "0x80 - Statistical Check Poker Count 1 and 0 Register"]
190 #[inline(always)]
191 pub const fn pkrcnt10(&self) -> &Pkrcnt10 {
192 &self.pkrcnt10
193 }
194 #[doc = "0x84 - Statistical Check Poker Count 3 and 2 Register"]
195 #[inline(always)]
196 pub const fn pkrcnt32(&self) -> &Pkrcnt32 {
197 &self.pkrcnt32
198 }
199 #[doc = "0x88 - Statistical Check Poker Count 5 and 4 Register"]
200 #[inline(always)]
201 pub const fn pkrcnt54(&self) -> &Pkrcnt54 {
202 &self.pkrcnt54
203 }
204 #[doc = "0x8c - Statistical Check Poker Count 7 and 6 Register"]
205 #[inline(always)]
206 pub const fn pkrcnt76(&self) -> &Pkrcnt76 {
207 &self.pkrcnt76
208 }
209 #[doc = "0x90 - Statistical Check Poker Count 9 and 8 Register"]
210 #[inline(always)]
211 pub const fn pkrcnt98(&self) -> &Pkrcnt98 {
212 &self.pkrcnt98
213 }
214 #[doc = "0x94 - Statistical Check Poker Count B and A Register"]
215 #[inline(always)]
216 pub const fn pkrcntba(&self) -> &Pkrcntba {
217 &self.pkrcntba
218 }
219 #[doc = "0x98 - Statistical Check Poker Count D and C Register"]
220 #[inline(always)]
221 pub const fn pkrcntdc(&self) -> &Pkrcntdc {
222 &self.pkrcntdc
223 }
224 #[doc = "0x9c - Statistical Check Poker Count F and E Register"]
225 #[inline(always)]
226 pub const fn pkrcntfe(&self) -> &Pkrcntfe {
227 &self.pkrcntfe
228 }
229 #[doc = "0xa0 - Security Configuration Register"]
230 #[inline(always)]
231 pub const fn sec_cfg(&self) -> &SecCfg {
232 &self.sec_cfg
233 }
234 #[doc = "0xa4 - Interrupt Control Register"]
235 #[inline(always)]
236 pub const fn int_ctrl(&self) -> &IntCtrl {
237 &self.int_ctrl
238 }
239 #[doc = "0xa8 - Mask Register"]
240 #[inline(always)]
241 pub const fn int_mask(&self) -> &IntMask {
242 &self.int_mask
243 }
244 #[doc = "0xac - Interrupt Status Register"]
245 #[inline(always)]
246 pub const fn int_status(&self) -> &IntStatus {
247 &self.int_status
248 }
249 #[doc = "0xb0 - Common Security Error Register"]
250 #[inline(always)]
251 pub const fn cser(&self) -> &Cser {
252 &self.cser
253 }
254 #[doc = "0xb4 - Common Security Clear Register"]
255 #[inline(always)]
256 pub const fn csclr(&self) -> &Csclr {
257 &self.csclr
258 }
259 #[doc = "0xec - TRNG Oscillator 2 Control Register"]
260 #[inline(always)]
261 pub const fn osc2_ctl(&self) -> &Osc2Ctl {
262 &self.osc2_ctl
263 }
264 #[doc = "0xf0 - Version ID Register (MS)"]
265 #[inline(always)]
266 pub const fn vid1(&self) -> &Vid1 {
267 &self.vid1
268 }
269 #[doc = "0xf4 - Version ID Register (LS)"]
270 #[inline(always)]
271 pub const fn vid2(&self) -> &Vid2 {
272 &self.vid2
273 }
274}
275#[doc = "MCTL (rw) register accessor: Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctl`] module"]
276#[doc(alias = "MCTL")]
277pub type Mctl = crate::Reg<mctl::MctlSpec>;
278#[doc = "Miscellaneous Control Register"]
279pub mod mctl;
280#[doc = "SCMISC (rw) register accessor: Statistical Check Miscellaneous Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmisc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scmisc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scmisc`] module"]
281#[doc(alias = "SCMISC")]
282pub type Scmisc = crate::Reg<scmisc::ScmiscSpec>;
283#[doc = "Statistical Check Miscellaneous Register"]
284pub mod scmisc;
285#[doc = "PKRRNG (rw) register accessor: Poker Range Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrrng::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrrng::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrrng`] module"]
286#[doc(alias = "PKRRNG")]
287pub type Pkrrng = crate::Reg<pkrrng::PkrrngSpec>;
288#[doc = "Poker Range Register"]
289pub mod pkrrng;
290#[doc = "PKRMAX (rw) register accessor: Poker Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrmax::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrmax::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrmax`] module"]
291#[doc(alias = "PKRMAX")]
292pub type Pkrmax = crate::Reg<pkrmax::PkrmaxSpec>;
293#[doc = "Poker Maximum Limit Register"]
294pub mod pkrmax;
295#[doc = "PKRSQ (r) register accessor: Poker Square Calculation Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrsq::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrsq`] module"]
296#[doc(alias = "PKRSQ")]
297pub type Pkrsq = crate::Reg<pkrsq::PkrsqSpec>;
298#[doc = "Poker Square Calculation Result Register"]
299pub mod pkrsq;
300#[doc = "SDCTL (rw) register accessor: Seed Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdctl`] module"]
301#[doc(alias = "SDCTL")]
302pub type Sdctl = crate::Reg<sdctl::SdctlSpec>;
303#[doc = "Seed Control Register"]
304pub mod sdctl;
305#[doc = "SBLIM (rw) register accessor: Sparse Bit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sblim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sblim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sblim`] module"]
306#[doc(alias = "SBLIM")]
307pub type Sblim = crate::Reg<sblim::SblimSpec>;
308#[doc = "Sparse Bit Limit Register"]
309pub mod sblim;
310#[doc = "TOTSAM (r) register accessor: Total Samples Register\n\nYou can [`read`](crate::Reg::read) this register and get [`totsam::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@totsam`] module"]
311#[doc(alias = "TOTSAM")]
312pub type Totsam = crate::Reg<totsam::TotsamSpec>;
313#[doc = "Total Samples Register"]
314pub mod totsam;
315#[doc = "FRQMIN (rw) register accessor: Frequency Count Minimum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqmin`] module"]
316#[doc(alias = "FRQMIN")]
317pub type Frqmin = crate::Reg<frqmin::FrqminSpec>;
318#[doc = "Frequency Count Minimum Limit Register"]
319pub mod frqmin;
320#[doc = "OSC2_FRQCNT (r) register accessor: Oscillator-2 Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_frqcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc2_frqcnt`] module"]
321#[doc(alias = "OSC2_FRQCNT")]
322pub type Osc2Frqcnt = crate::Reg<osc2_frqcnt::Osc2FrqcntSpec>;
323#[doc = "Oscillator-2 Frequency Count Register"]
324pub mod osc2_frqcnt;
325#[doc = "FRQCNT (r) register accessor: Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqcnt`] module"]
326#[doc(alias = "FRQCNT")]
327pub type Frqcnt = crate::Reg<frqcnt::FrqcntSpec>;
328#[doc = "Frequency Count Register"]
329pub mod frqcnt;
330#[doc = "FRQMAX (rw) register accessor: Frequency Count Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmax::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmax::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqmax`] module"]
331#[doc(alias = "FRQMAX")]
332pub type Frqmax = crate::Reg<frqmax::FrqmaxSpec>;
333#[doc = "Frequency Count Maximum Limit Register"]
334pub mod frqmax;
335#[doc = "SCMC (r) register accessor: Statistical Check Monobit Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scmc`] module"]
336#[doc(alias = "SCMC")]
337pub type Scmc = crate::Reg<scmc::ScmcSpec>;
338#[doc = "Statistical Check Monobit Count Register"]
339pub mod scmc;
340#[doc = "SCML (rw) register accessor: Statistical Check Monobit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scml::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scml::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scml`] module"]
341#[doc(alias = "SCML")]
342pub type Scml = crate::Reg<scml::ScmlSpec>;
343#[doc = "Statistical Check Monobit Limit Register"]
344pub mod scml;
345#[doc = "SCR1C (r) register accessor: Statistical Check Run Length 1 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr1c`] module"]
346#[doc(alias = "SCR1C")]
347pub type Scr1c = crate::Reg<scr1c::Scr1cSpec>;
348#[doc = "Statistical Check Run Length 1 Count Register"]
349pub mod scr1c;
350#[doc = "SCR1L (rw) register accessor: Statistical Check Run Length 1 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr1l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr1l`] module"]
351#[doc(alias = "SCR1L")]
352pub type Scr1l = crate::Reg<scr1l::Scr1lSpec>;
353#[doc = "Statistical Check Run Length 1 Limit Register"]
354pub mod scr1l;
355#[doc = "SCR2C (r) register accessor: Statistical Check Run Length 2 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr2c`] module"]
356#[doc(alias = "SCR2C")]
357pub type Scr2c = crate::Reg<scr2c::Scr2cSpec>;
358#[doc = "Statistical Check Run Length 2 Count Register"]
359pub mod scr2c;
360#[doc = "SCR2L (rw) register accessor: Statistical Check Run Length 2 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr2l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr2l`] module"]
361#[doc(alias = "SCR2L")]
362pub type Scr2l = crate::Reg<scr2l::Scr2lSpec>;
363#[doc = "Statistical Check Run Length 2 Limit Register"]
364pub mod scr2l;
365#[doc = "SCR3C (r) register accessor: Statistical Check Run Length 3 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr3c`] module"]
366#[doc(alias = "SCR3C")]
367pub type Scr3c = crate::Reg<scr3c::Scr3cSpec>;
368#[doc = "Statistical Check Run Length 3 Count Register"]
369pub mod scr3c;
370#[doc = "SCR3L (rw) register accessor: Statistical Check Run Length 3 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr3l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr3l`] module"]
371#[doc(alias = "SCR3L")]
372pub type Scr3l = crate::Reg<scr3l::Scr3lSpec>;
373#[doc = "Statistical Check Run Length 3 Limit Register"]
374pub mod scr3l;
375#[doc = "SCR4C (r) register accessor: Statistical Check Run Length 4 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr4c`] module"]
376#[doc(alias = "SCR4C")]
377pub type Scr4c = crate::Reg<scr4c::Scr4cSpec>;
378#[doc = "Statistical Check Run Length 4 Count Register"]
379pub mod scr4c;
380#[doc = "SCR4L (rw) register accessor: Statistical Check Run Length 4 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr4l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr4l`] module"]
381#[doc(alias = "SCR4L")]
382pub type Scr4l = crate::Reg<scr4l::Scr4lSpec>;
383#[doc = "Statistical Check Run Length 4 Limit Register"]
384pub mod scr4l;
385#[doc = "SCR5C (r) register accessor: Statistical Check Run Length 5 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr5c`] module"]
386#[doc(alias = "SCR5C")]
387pub type Scr5c = crate::Reg<scr5c::Scr5cSpec>;
388#[doc = "Statistical Check Run Length 5 Count Register"]
389pub mod scr5c;
390#[doc = "SCR5L (rw) register accessor: Statistical Check Run Length 5 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr5l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr5l`] module"]
391#[doc(alias = "SCR5L")]
392pub type Scr5l = crate::Reg<scr5l::Scr5lSpec>;
393#[doc = "Statistical Check Run Length 5 Limit Register"]
394pub mod scr5l;
395#[doc = "SCR6PC (r) register accessor: Statistical Check Run Length 6+ Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr6pc`] module"]
396#[doc(alias = "SCR6PC")]
397pub type Scr6pc = crate::Reg<scr6pc::Scr6pcSpec>;
398#[doc = "Statistical Check Run Length 6+ Count Register"]
399pub mod scr6pc;
400#[doc = "SCR6PL (rw) register accessor: Statistical Check Run Length 6+ Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr6pl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr6pl`] module"]
401#[doc(alias = "SCR6PL")]
402pub type Scr6pl = crate::Reg<scr6pl::Scr6plSpec>;
403#[doc = "Statistical Check Run Length 6+ Limit Register"]
404pub mod scr6pl;
405#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
406#[doc(alias = "STATUS")]
407pub type Status = crate::Reg<status::StatusSpec>;
408#[doc = "Status Register"]
409pub mod status;
410#[doc = "ENT (rw) register accessor: Entropy Read Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ent::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ent::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ent`] module"]
411#[doc(alias = "ENT")]
412pub type Ent = crate::Reg<ent::EntSpec>;
413#[doc = "Entropy Read Register"]
414pub mod ent;
415#[doc = "PKRCNT10 (r) register accessor: Statistical Check Poker Count 1 and 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt10`] module"]
416#[doc(alias = "PKRCNT10")]
417pub type Pkrcnt10 = crate::Reg<pkrcnt10::Pkrcnt10Spec>;
418#[doc = "Statistical Check Poker Count 1 and 0 Register"]
419pub mod pkrcnt10;
420#[doc = "PKRCNT32 (r) register accessor: Statistical Check Poker Count 3 and 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt32::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt32`] module"]
421#[doc(alias = "PKRCNT32")]
422pub type Pkrcnt32 = crate::Reg<pkrcnt32::Pkrcnt32Spec>;
423#[doc = "Statistical Check Poker Count 3 and 2 Register"]
424pub mod pkrcnt32;
425#[doc = "PKRCNT54 (r) register accessor: Statistical Check Poker Count 5 and 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt54::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt54`] module"]
426#[doc(alias = "PKRCNT54")]
427pub type Pkrcnt54 = crate::Reg<pkrcnt54::Pkrcnt54Spec>;
428#[doc = "Statistical Check Poker Count 5 and 4 Register"]
429pub mod pkrcnt54;
430#[doc = "PKRCNT76 (r) register accessor: Statistical Check Poker Count 7 and 6 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt76::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt76`] module"]
431#[doc(alias = "PKRCNT76")]
432pub type Pkrcnt76 = crate::Reg<pkrcnt76::Pkrcnt76Spec>;
433#[doc = "Statistical Check Poker Count 7 and 6 Register"]
434pub mod pkrcnt76;
435#[doc = "PKRCNT98 (r) register accessor: Statistical Check Poker Count 9 and 8 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt98::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt98`] module"]
436#[doc(alias = "PKRCNT98")]
437pub type Pkrcnt98 = crate::Reg<pkrcnt98::Pkrcnt98Spec>;
438#[doc = "Statistical Check Poker Count 9 and 8 Register"]
439pub mod pkrcnt98;
440#[doc = "PKRCNTBA (r) register accessor: Statistical Check Poker Count B and A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntba::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntba`] module"]
441#[doc(alias = "PKRCNTBA")]
442pub type Pkrcntba = crate::Reg<pkrcntba::PkrcntbaSpec>;
443#[doc = "Statistical Check Poker Count B and A Register"]
444pub mod pkrcntba;
445#[doc = "PKRCNTDC (r) register accessor: Statistical Check Poker Count D and C Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntdc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntdc`] module"]
446#[doc(alias = "PKRCNTDC")]
447pub type Pkrcntdc = crate::Reg<pkrcntdc::PkrcntdcSpec>;
448#[doc = "Statistical Check Poker Count D and C Register"]
449pub mod pkrcntdc;
450#[doc = "PKRCNTFE (r) register accessor: Statistical Check Poker Count F and E Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntfe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntfe`] module"]
451#[doc(alias = "PKRCNTFE")]
452pub type Pkrcntfe = crate::Reg<pkrcntfe::PkrcntfeSpec>;
453#[doc = "Statistical Check Poker Count F and E Register"]
454pub mod pkrcntfe;
455#[doc = "SEC_CFG (rw) register accessor: Security Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_cfg`] module"]
456#[doc(alias = "SEC_CFG")]
457pub type SecCfg = crate::Reg<sec_cfg::SecCfgSpec>;
458#[doc = "Security Configuration Register"]
459pub mod sec_cfg;
460#[doc = "INT_CTRL (rw) register accessor: Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ctrl`] module"]
461#[doc(alias = "INT_CTRL")]
462pub type IntCtrl = crate::Reg<int_ctrl::IntCtrlSpec>;
463#[doc = "Interrupt Control Register"]
464pub mod int_ctrl;
465#[doc = "INT_MASK (rw) register accessor: Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_mask`] module"]
466#[doc(alias = "INT_MASK")]
467pub type IntMask = crate::Reg<int_mask::IntMaskSpec>;
468#[doc = "Mask Register"]
469pub mod int_mask;
470#[doc = "INT_STATUS (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"]
471#[doc(alias = "INT_STATUS")]
472pub type IntStatus = crate::Reg<int_status::IntStatusSpec>;
473#[doc = "Interrupt Status Register"]
474pub mod int_status;
475#[doc = "CSER (r) register accessor: Common Security Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cser::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cser`] module"]
476#[doc(alias = "CSER")]
477pub type Cser = crate::Reg<cser::CserSpec>;
478#[doc = "Common Security Error Register"]
479pub mod cser;
480#[doc = "CSCLR (w) register accessor: Common Security Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csclr`] module"]
481#[doc(alias = "CSCLR")]
482pub type Csclr = crate::Reg<csclr::CsclrSpec>;
483#[doc = "Common Security Clear Register"]
484pub mod csclr;
485#[doc = "OSC2_CTL (rw) register accessor: TRNG Oscillator 2 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc2_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc2_ctl`] module"]
486#[doc(alias = "OSC2_CTL")]
487pub type Osc2Ctl = crate::Reg<osc2_ctl::Osc2CtlSpec>;
488#[doc = "TRNG Oscillator 2 Control Register"]
489pub mod osc2_ctl;
490#[doc = "VID1 (r) register accessor: Version ID Register (MS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid1`] module"]
491#[doc(alias = "VID1")]
492pub type Vid1 = crate::Reg<vid1::Vid1Spec>;
493#[doc = "Version ID Register (MS)"]
494pub mod vid1;
495#[doc = "VID2 (r) register accessor: Version ID Register (LS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid2`] module"]
496#[doc(alias = "VID2")]
497pub type Vid2 = crate::Reg<vid2::Vid2Spec>;
498#[doc = "Version ID Register (LS)"]
499pub mod vid2;