mcxa_pac/syscon/
swd_access_cpu0.rs

1#[doc = "Register `SWD_ACCESS_CPU0` reader"]
2pub type R = crate::R<SwdAccessCpu0Spec>;
3#[doc = "Register `SWD_ACCESS_CPU0` writer"]
4pub type W = crate::W<SwdAccessCpu0Spec>;
5#[doc = "CPU0 SWD-AP: 0x12345678\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u32)]
9pub enum SecCode {
10    #[doc = "0: CPU0 DAP is not allowed. Reading back register is read as 0x5."]
11    Disable = 0,
12    #[doc = "305419896: Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."]
13    Enable = 305419896,
14}
15impl From<SecCode> for u32 {
16    #[inline(always)]
17    fn from(variant: SecCode) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for SecCode {
22    type Ux = u32;
23}
24impl crate::IsEnum for SecCode {}
25#[doc = "Field `SEC_CODE` reader - CPU0 SWD-AP: 0x12345678"]
26pub type SecCodeR = crate::FieldReader<SecCode>;
27impl SecCodeR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<SecCode> {
31        match self.bits {
32            0 => Some(SecCode::Disable),
33            305419896 => Some(SecCode::Enable),
34            _ => None,
35        }
36    }
37    #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."]
38    #[inline(always)]
39    pub fn is_disable(&self) -> bool {
40        *self == SecCode::Disable
41    }
42    #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."]
43    #[inline(always)]
44    pub fn is_enable(&self) -> bool {
45        *self == SecCode::Enable
46    }
47}
48#[doc = "Field `SEC_CODE` writer - CPU0 SWD-AP: 0x12345678"]
49pub type SecCodeW<'a, REG> = crate::FieldWriter<'a, REG, 32, SecCode>;
50impl<'a, REG> SecCodeW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u32>,
54{
55    #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."]
56    #[inline(always)]
57    pub fn disable(self) -> &'a mut crate::W<REG> {
58        self.variant(SecCode::Disable)
59    }
60    #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."]
61    #[inline(always)]
62    pub fn enable(self) -> &'a mut crate::W<REG> {
63        self.variant(SecCode::Enable)
64    }
65}
66impl R {
67    #[doc = "Bits 0:31 - CPU0 SWD-AP: 0x12345678"]
68    #[inline(always)]
69    pub fn sec_code(&self) -> SecCodeR {
70        SecCodeR::new(self.bits)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("SWD_ACCESS_CPU0")
77            .field("sec_code", &self.sec_code())
78            .finish()
79    }
80}
81impl W {
82    #[doc = "Bits 0:31 - CPU0 SWD-AP: 0x12345678"]
83    #[inline(always)]
84    pub fn sec_code(&mut self) -> SecCodeW<'_, SwdAccessCpu0Spec> {
85        SecCodeW::new(self, 0)
86    }
87}
88#[doc = "CPU0 Software Debug Access\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_access_cpu0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_access_cpu0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct SwdAccessCpu0Spec;
90impl crate::RegisterSpec for SwdAccessCpu0Spec {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`swd_access_cpu0::R`](R) reader structure"]
94impl crate::Readable for SwdAccessCpu0Spec {}
95#[doc = "`write(|w| ..)` method takes [`swd_access_cpu0::W`](W) writer structure"]
96impl crate::Writable for SwdAccessCpu0Spec {
97    type Safety = crate::Unsafe;
98}
99#[doc = "`reset()` method sets SWD_ACCESS_CPU0 to value 0"]
100impl crate::Resettable for SwdAccessCpu0Spec {}
mcxa_pac/syscon/swd_access_cpu0.rs

mcxa_pac/syscon/
swd_access_cpu0.rs
