mcxa_pac/syscon/
slowclkdiv.rs

1#[doc = "Register `SLOWCLKDIV` reader"]
2pub type R = crate::R<SlowclkdivSpec>;
3#[doc = "Register `SLOWCLKDIV` writer"]
4pub type W = crate::W<SlowclkdivSpec>;
5#[doc = "Field `DIV` reader - Clock divider value"]
6pub type DivR = crate::FieldReader;
7#[doc = "Resets the divider counter\n\nValue on reset: 0"]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum Reset {
11    #[doc = "0: Divider is not reset"]
12    Released = 0,
13    #[doc = "1: Divider is reset"]
14    Asserted = 1,
15}
16impl From<Reset> for bool {
17    #[inline(always)]
18    fn from(variant: Reset) -> Self {
19        variant as u8 != 0
20    }
21}
22#[doc = "Field `RESET` reader - Resets the divider counter"]
23pub type ResetR = crate::BitReader<Reset>;
24impl ResetR {
25    #[doc = "Get enumerated values variant"]
26    #[inline(always)]
27    pub const fn variant(&self) -> Reset {
28        match self.bits {
29            false => Reset::Released,
30            true => Reset::Asserted,
31        }
32    }
33    #[doc = "Divider is not reset"]
34    #[inline(always)]
35    pub fn is_released(&self) -> bool {
36        *self == Reset::Released
37    }
38    #[doc = "Divider is reset"]
39    #[inline(always)]
40    pub fn is_asserted(&self) -> bool {
41        *self == Reset::Asserted
42    }
43}
44#[doc = "Field `RESET` writer - Resets the divider counter"]
45pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>;
46impl<'a, REG> ResetW<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    #[doc = "Divider is not reset"]
51    #[inline(always)]
52    pub fn released(self) -> &'a mut crate::W<REG> {
53        self.variant(Reset::Released)
54    }
55    #[doc = "Divider is reset"]
56    #[inline(always)]
57    pub fn asserted(self) -> &'a mut crate::W<REG> {
58        self.variant(Reset::Asserted)
59    }
60}
61#[doc = "Halts the divider counter\n\nValue on reset: 0"]
62#[cfg_attr(feature = "defmt", derive(defmt::Format))]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum Halt {
65    #[doc = "0: Divider clock is running"]
66    Run = 0,
67    #[doc = "1: Divider clock is stopped"]
68    Halt = 1,
69}
70impl From<Halt> for bool {
71    #[inline(always)]
72    fn from(variant: Halt) -> Self {
73        variant as u8 != 0
74    }
75}
76#[doc = "Field `HALT` reader - Halts the divider counter"]
77pub type HaltR = crate::BitReader<Halt>;
78impl HaltR {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> Halt {
82        match self.bits {
83            false => Halt::Run,
84            true => Halt::Halt,
85        }
86    }
87    #[doc = "Divider clock is running"]
88    #[inline(always)]
89    pub fn is_run(&self) -> bool {
90        *self == Halt::Run
91    }
92    #[doc = "Divider clock is stopped"]
93    #[inline(always)]
94    pub fn is_halt(&self) -> bool {
95        *self == Halt::Halt
96    }
97}
98#[doc = "Field `HALT` writer - Halts the divider counter"]
99pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>;
100impl<'a, REG> HaltW<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Divider clock is running"]
105    #[inline(always)]
106    pub fn run(self) -> &'a mut crate::W<REG> {
107        self.variant(Halt::Run)
108    }
109    #[doc = "Divider clock is stopped"]
110    #[inline(always)]
111    pub fn halt(self) -> &'a mut crate::W<REG> {
112        self.variant(Halt::Halt)
113    }
114}
115#[doc = "Divider status flag\n\nValue on reset: 0"]
116#[cfg_attr(feature = "defmt", derive(defmt::Format))]
117#[derive(Clone, Copy, Debug, PartialEq, Eq)]
118pub enum Unstab {
119    #[doc = "0: Divider clock is stable"]
120    Stable = 0,
121    #[doc = "1: Clock frequency is not stable"]
122    Ongoing = 1,
123}
124impl From<Unstab> for bool {
125    #[inline(always)]
126    fn from(variant: Unstab) -> Self {
127        variant as u8 != 0
128    }
129}
130#[doc = "Field `UNSTAB` reader - Divider status flag"]
131pub type UnstabR = crate::BitReader<Unstab>;
132impl UnstabR {
133    #[doc = "Get enumerated values variant"]
134    #[inline(always)]
135    pub const fn variant(&self) -> Unstab {
136        match self.bits {
137            false => Unstab::Stable,
138            true => Unstab::Ongoing,
139        }
140    }
141    #[doc = "Divider clock is stable"]
142    #[inline(always)]
143    pub fn is_stable(&self) -> bool {
144        *self == Unstab::Stable
145    }
146    #[doc = "Clock frequency is not stable"]
147    #[inline(always)]
148    pub fn is_ongoing(&self) -> bool {
149        *self == Unstab::Ongoing
150    }
151}
152impl R {
153    #[doc = "Bits 0:7 - Clock divider value"]
154    #[inline(always)]
155    pub fn div(&self) -> DivR {
156        DivR::new((self.bits & 0xff) as u8)
157    }
158    #[doc = "Bit 29 - Resets the divider counter"]
159    #[inline(always)]
160    pub fn reset(&self) -> ResetR {
161        ResetR::new(((self.bits >> 29) & 1) != 0)
162    }
163    #[doc = "Bit 30 - Halts the divider counter"]
164    #[inline(always)]
165    pub fn halt(&self) -> HaltR {
166        HaltR::new(((self.bits >> 30) & 1) != 0)
167    }
168    #[doc = "Bit 31 - Divider status flag"]
169    #[inline(always)]
170    pub fn unstab(&self) -> UnstabR {
171        UnstabR::new(((self.bits >> 31) & 1) != 0)
172    }
173}
174#[cfg(feature = "debug")]
175impl core::fmt::Debug for R {
176    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
177        f.debug_struct("SLOWCLKDIV")
178            .field("div", &self.div())
179            .field("reset", &self.reset())
180            .field("halt", &self.halt())
181            .field("unstab", &self.unstab())
182            .finish()
183    }
184}
185impl W {
186    #[doc = "Bit 29 - Resets the divider counter"]
187    #[inline(always)]
188    pub fn reset(&mut self) -> ResetW<'_, SlowclkdivSpec> {
189        ResetW::new(self, 29)
190    }
191    #[doc = "Bit 30 - Halts the divider counter"]
192    #[inline(always)]
193    pub fn halt(&mut self) -> HaltW<'_, SlowclkdivSpec> {
194        HaltW::new(self, 30)
195    }
196}
197#[doc = "SLOW_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`slowclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slowclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
198pub struct SlowclkdivSpec;
199impl crate::RegisterSpec for SlowclkdivSpec {
200    type Ux = u32;
201}
202#[doc = "`read()` method returns [`slowclkdiv::R`](R) reader structure"]
203impl crate::Readable for SlowclkdivSpec {}
204#[doc = "`write(|w| ..)` method takes [`slowclkdiv::W`](W) writer structure"]
205impl crate::Writable for SlowclkdivSpec {
206    type Safety = crate::Unsafe;
207}
208#[doc = "`reset()` method sets SLOWCLKDIV to value 0x05"]
209impl crate::Resettable for SlowclkdivSpec {
210    const RESET_VALUE: u32 = 0x05;
211}
mcxa_pac/syscon/slowclkdiv.rs

mcxa_pac/syscon/
slowclkdiv.rs
