mcxa_pac/syscon/
ram_interleave.rs

1#[doc = "Register `RAM_INTERLEAVE` reader"]
2pub type R = crate::R<RamInterleaveSpec>;
3#[doc = "Register `RAM_INTERLEAVE` writer"]
4pub type W = crate::W<RamInterleaveSpec>;
5#[doc = "Controls RAM access for RAMA1 and RAMA2\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Interleave {
9    #[doc = "0: RAM access is consecutive."]
10    Normal = 0,
11    #[doc = "1: RAM access is interleaved. This setting is need for PKC L0 memory access."]
12    Interleave = 1,
13}
14impl From<Interleave> for bool {
15    #[inline(always)]
16    fn from(variant: Interleave) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `INTERLEAVE` reader - Controls RAM access for RAMA1 and RAMA2"]
21pub type InterleaveR = crate::BitReader<Interleave>;
22impl InterleaveR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Interleave {
26        match self.bits {
27            false => Interleave::Normal,
28            true => Interleave::Interleave,
29        }
30    }
31    #[doc = "RAM access is consecutive."]
32    #[inline(always)]
33    pub fn is_normal(&self) -> bool {
34        *self == Interleave::Normal
35    }
36    #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."]
37    #[inline(always)]
38    pub fn is_interleave(&self) -> bool {
39        *self == Interleave::Interleave
40    }
41}
42#[doc = "Field `INTERLEAVE` writer - Controls RAM access for RAMA1 and RAMA2"]
43pub type InterleaveW<'a, REG> = crate::BitWriter<'a, REG, Interleave>;
44impl<'a, REG> InterleaveW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "RAM access is consecutive."]
49    #[inline(always)]
50    pub fn normal(self) -> &'a mut crate::W<REG> {
51        self.variant(Interleave::Normal)
52    }
53    #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."]
54    #[inline(always)]
55    pub fn interleave(self) -> &'a mut crate::W<REG> {
56        self.variant(Interleave::Interleave)
57    }
58}
59impl R {
60    #[doc = "Bit 0 - Controls RAM access for RAMA1 and RAMA2"]
61    #[inline(always)]
62    pub fn interleave(&self) -> InterleaveR {
63        InterleaveR::new((self.bits & 1) != 0)
64    }
65}
66#[cfg(feature = "debug")]
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("RAM_INTERLEAVE")
70            .field("interleave", &self.interleave())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - Controls RAM access for RAMA1 and RAMA2"]
76    #[inline(always)]
77    pub fn interleave(&mut self) -> InterleaveW<'_, RamInterleaveSpec> {
78        InterleaveW::new(self, 0)
79    }
80}
81#[doc = "Controls RAM Interleave Integration\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_interleave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_interleave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
82pub struct RamInterleaveSpec;
83impl crate::RegisterSpec for RamInterleaveSpec {
84    type Ux = u32;
85}
86#[doc = "`read()` method returns [`ram_interleave::R`](R) reader structure"]
87impl crate::Readable for RamInterleaveSpec {}
88#[doc = "`write(|w| ..)` method takes [`ram_interleave::W`](W) writer structure"]
89impl crate::Writable for RamInterleaveSpec {
90    type Safety = crate::Unsafe;
91}
92#[doc = "`reset()` method sets RAM_INTERLEAVE to value 0"]
93impl crate::Resettable for RamInterleaveSpec {}
mcxa_pac/syscon/ram_interleave.rs

mcxa_pac/syscon/
ram_interleave.rs
