mcxa_pac/spc0/
vd_sys_cfg.rs

1#[doc = "Register `VD_SYS_CFG` reader"]
2pub type R = crate::R<VdSysCfgSpec>;
3#[doc = "Register `VD_SYS_CFG` writer"]
4pub type W = crate::W<VdSysCfgSpec>;
5#[doc = "System LVD Reset Enable\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Lvdre {
9    #[doc = "0: Disable"]
10    Disable = 0,
11    #[doc = "1: Enable"]
12    Enable = 1,
13}
14impl From<Lvdre> for bool {
15    #[inline(always)]
16    fn from(variant: Lvdre) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `LVDRE` reader - System LVD Reset Enable"]
21pub type LvdreR = crate::BitReader<Lvdre>;
22impl LvdreR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Lvdre {
26        match self.bits {
27            false => Lvdre::Disable,
28            true => Lvdre::Enable,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Lvdre::Disable
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Lvdre::Enable
40    }
41}
42#[doc = "Field `LVDRE` writer - System LVD Reset Enable"]
43pub type LvdreW<'a, REG> = crate::BitWriter<'a, REG, Lvdre>;
44impl<'a, REG> LvdreW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Lvdre::Disable)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Lvdre::Enable)
57    }
58}
59#[doc = "System LVD Interrupt Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Lvdie {
63    #[doc = "0: Disable"]
64    Disable = 0,
65    #[doc = "1: Enable"]
66    Enable = 1,
67}
68impl From<Lvdie> for bool {
69    #[inline(always)]
70    fn from(variant: Lvdie) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `LVDIE` reader - System LVD Interrupt Enable"]
75pub type LvdieR = crate::BitReader<Lvdie>;
76impl LvdieR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Lvdie {
80        match self.bits {
81            false => Lvdie::Disable,
82            true => Lvdie::Enable,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Lvdie::Disable
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Lvdie::Enable
94    }
95}
96#[doc = "Field `LVDIE` writer - System LVD Interrupt Enable"]
97pub type LvdieW<'a, REG> = crate::BitWriter<'a, REG, Lvdie>;
98impl<'a, REG> LvdieW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Lvdie::Disable)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Lvdie::Enable)
111    }
112}
113#[doc = "System HVD Reset Enable\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Hvdre {
117    #[doc = "0: Disable"]
118    Disable = 0,
119    #[doc = "1: Enable"]
120    Enable = 1,
121}
122impl From<Hvdre> for bool {
123    #[inline(always)]
124    fn from(variant: Hvdre) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `HVDRE` reader - System HVD Reset Enable"]
129pub type HvdreR = crate::BitReader<Hvdre>;
130impl HvdreR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Hvdre {
134        match self.bits {
135            false => Hvdre::Disable,
136            true => Hvdre::Enable,
137        }
138    }
139    #[doc = "Disable"]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == Hvdre::Disable
143    }
144    #[doc = "Enable"]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == Hvdre::Enable
148    }
149}
150#[doc = "Field `HVDRE` writer - System HVD Reset Enable"]
151pub type HvdreW<'a, REG> = crate::BitWriter<'a, REG, Hvdre>;
152impl<'a, REG> HvdreW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Disable"]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(Hvdre::Disable)
160    }
161    #[doc = "Enable"]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(Hvdre::Enable)
165    }
166}
167#[doc = "System HVD Interrupt Enable\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Hvdie {
171    #[doc = "0: Disable"]
172    Disable = 0,
173    #[doc = "1: Enable"]
174    Enable = 1,
175}
176impl From<Hvdie> for bool {
177    #[inline(always)]
178    fn from(variant: Hvdie) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `HVDIE` reader - System HVD Interrupt Enable"]
183pub type HvdieR = crate::BitReader<Hvdie>;
184impl HvdieR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Hvdie {
188        match self.bits {
189            false => Hvdie::Disable,
190            true => Hvdie::Enable,
191        }
192    }
193    #[doc = "Disable"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == Hvdie::Disable
197    }
198    #[doc = "Enable"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == Hvdie::Enable
202    }
203}
204#[doc = "Field `HVDIE` writer - System HVD Interrupt Enable"]
205pub type HvdieW<'a, REG> = crate::BitWriter<'a, REG, Hvdie>;
206impl<'a, REG> HvdieW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Disable"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(Hvdie::Disable)
214    }
215    #[doc = "Enable"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(Hvdie::Enable)
219    }
220}
221#[doc = "System Voltage Detect Reset Enable Lock\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Lock {
225    #[doc = "0: Allow"]
226    Allow = 0,
227    #[doc = "1: Deny"]
228    Deny = 1,
229}
230impl From<Lock> for bool {
231    #[inline(always)]
232    fn from(variant: Lock) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `LOCK` reader - System Voltage Detect Reset Enable Lock"]
237pub type LockR = crate::BitReader<Lock>;
238impl LockR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Lock {
242        match self.bits {
243            false => Lock::Allow,
244            true => Lock::Deny,
245        }
246    }
247    #[doc = "Allow"]
248    #[inline(always)]
249    pub fn is_allow(&self) -> bool {
250        *self == Lock::Allow
251    }
252    #[doc = "Deny"]
253    #[inline(always)]
254    pub fn is_deny(&self) -> bool {
255        *self == Lock::Deny
256    }
257}
258#[doc = "Field `LOCK` writer - System Voltage Detect Reset Enable Lock"]
259pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>;
260impl<'a, REG> LockW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Allow"]
265    #[inline(always)]
266    pub fn allow(self) -> &'a mut crate::W<REG> {
267        self.variant(Lock::Allow)
268    }
269    #[doc = "Deny"]
270    #[inline(always)]
271    pub fn deny(self) -> &'a mut crate::W<REG> {
272        self.variant(Lock::Deny)
273    }
274}
275impl R {
276    #[doc = "Bit 0 - System LVD Reset Enable"]
277    #[inline(always)]
278    pub fn lvdre(&self) -> LvdreR {
279        LvdreR::new((self.bits & 1) != 0)
280    }
281    #[doc = "Bit 1 - System LVD Interrupt Enable"]
282    #[inline(always)]
283    pub fn lvdie(&self) -> LvdieR {
284        LvdieR::new(((self.bits >> 1) & 1) != 0)
285    }
286    #[doc = "Bit 2 - System HVD Reset Enable"]
287    #[inline(always)]
288    pub fn hvdre(&self) -> HvdreR {
289        HvdreR::new(((self.bits >> 2) & 1) != 0)
290    }
291    #[doc = "Bit 3 - System HVD Interrupt Enable"]
292    #[inline(always)]
293    pub fn hvdie(&self) -> HvdieR {
294        HvdieR::new(((self.bits >> 3) & 1) != 0)
295    }
296    #[doc = "Bit 16 - System Voltage Detect Reset Enable Lock"]
297    #[inline(always)]
298    pub fn lock(&self) -> LockR {
299        LockR::new(((self.bits >> 16) & 1) != 0)
300    }
301}
302#[cfg(feature = "debug")]
303impl core::fmt::Debug for R {
304    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
305        f.debug_struct("VD_SYS_CFG")
306            .field("lvdre", &self.lvdre())
307            .field("lvdie", &self.lvdie())
308            .field("hvdre", &self.hvdre())
309            .field("hvdie", &self.hvdie())
310            .field("lock", &self.lock())
311            .finish()
312    }
313}
314impl W {
315    #[doc = "Bit 0 - System LVD Reset Enable"]
316    #[inline(always)]
317    pub fn lvdre(&mut self) -> LvdreW<'_, VdSysCfgSpec> {
318        LvdreW::new(self, 0)
319    }
320    #[doc = "Bit 1 - System LVD Interrupt Enable"]
321    #[inline(always)]
322    pub fn lvdie(&mut self) -> LvdieW<'_, VdSysCfgSpec> {
323        LvdieW::new(self, 1)
324    }
325    #[doc = "Bit 2 - System HVD Reset Enable"]
326    #[inline(always)]
327    pub fn hvdre(&mut self) -> HvdreW<'_, VdSysCfgSpec> {
328        HvdreW::new(self, 2)
329    }
330    #[doc = "Bit 3 - System HVD Interrupt Enable"]
331    #[inline(always)]
332    pub fn hvdie(&mut self) -> HvdieW<'_, VdSysCfgSpec> {
333        HvdieW::new(self, 3)
334    }
335    #[doc = "Bit 16 - System Voltage Detect Reset Enable Lock"]
336    #[inline(always)]
337    pub fn lock(&mut self) -> LockW<'_, VdSysCfgSpec> {
338        LockW::new(self, 16)
339    }
340}
341#[doc = "System Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_sys_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_sys_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
342pub struct VdSysCfgSpec;
343impl crate::RegisterSpec for VdSysCfgSpec {
344    type Ux = u32;
345}
346#[doc = "`read()` method returns [`vd_sys_cfg::R`](R) reader structure"]
347impl crate::Readable for VdSysCfgSpec {}
348#[doc = "`write(|w| ..)` method takes [`vd_sys_cfg::W`](W) writer structure"]
349impl crate::Writable for VdSysCfgSpec {
350    type Safety = crate::Unsafe;
351}
352#[doc = "`reset()` method sets VD_SYS_CFG to value 0x01"]
353impl crate::Resettable for VdSysCfgSpec {
354    const RESET_VALUE: u32 = 0x01;
355}
mcxa_pac/spc0/vd_sys_cfg.rs

mcxa_pac/spc0/
vd_sys_cfg.rs
