mcxa_pac/spc0/
active_cfg.rs

1#[doc = "Register `ACTIVE_CFG` reader"]
2pub type R = crate::R<ActiveCfgSpec>;
3#[doc = "Register `ACTIVE_CFG` writer"]
4pub type W = crate::W<ActiveCfgSpec>;
5#[doc = "LDO_CORE VDD Drive Strength\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CoreldoVddDs {
9    #[doc = "0: Low"]
10    Low = 0,
11    #[doc = "1: Normal"]
12    Normal = 1,
13}
14impl From<CoreldoVddDs> for bool {
15    #[inline(always)]
16    fn from(variant: CoreldoVddDs) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `CORELDO_VDD_DS` reader - LDO_CORE VDD Drive Strength"]
21pub type CoreldoVddDsR = crate::BitReader<CoreldoVddDs>;
22impl CoreldoVddDsR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> CoreldoVddDs {
26        match self.bits {
27            false => CoreldoVddDs::Low,
28            true => CoreldoVddDs::Normal,
29        }
30    }
31    #[doc = "Low"]
32    #[inline(always)]
33    pub fn is_low(&self) -> bool {
34        *self == CoreldoVddDs::Low
35    }
36    #[doc = "Normal"]
37    #[inline(always)]
38    pub fn is_normal(&self) -> bool {
39        *self == CoreldoVddDs::Normal
40    }
41}
42#[doc = "Field `CORELDO_VDD_DS` writer - LDO_CORE VDD Drive Strength"]
43pub type CoreldoVddDsW<'a, REG> = crate::BitWriter<'a, REG, CoreldoVddDs>;
44impl<'a, REG> CoreldoVddDsW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Low"]
49    #[inline(always)]
50    pub fn low(self) -> &'a mut crate::W<REG> {
51        self.variant(CoreldoVddDs::Low)
52    }
53    #[doc = "Normal"]
54    #[inline(always)]
55    pub fn normal(self) -> &'a mut crate::W<REG> {
56        self.variant(CoreldoVddDs::Normal)
57    }
58}
59#[doc = "LDO_CORE VDD Regulator Voltage Level\n\nValue on reset: 1"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum CoreldoVddLvl {
64    #[doc = "1: Regulate to mid voltage (1.0 V)"]
65    Mid = 1,
66    #[doc = "2: Regulate to normal voltage (1.1 V)"]
67    Normal = 2,
68    #[doc = "3: Regulate to overdrive voltage (1.15 V)"]
69    Over = 3,
70}
71impl From<CoreldoVddLvl> for u8 {
72    #[inline(always)]
73    fn from(variant: CoreldoVddLvl) -> Self {
74        variant as _
75    }
76}
77impl crate::FieldSpec for CoreldoVddLvl {
78    type Ux = u8;
79}
80impl crate::IsEnum for CoreldoVddLvl {}
81#[doc = "Field `CORELDO_VDD_LVL` reader - LDO_CORE VDD Regulator Voltage Level"]
82pub type CoreldoVddLvlR = crate::FieldReader<CoreldoVddLvl>;
83impl CoreldoVddLvlR {
84    #[doc = "Get enumerated values variant"]
85    #[inline(always)]
86    pub const fn variant(&self) -> Option<CoreldoVddLvl> {
87        match self.bits {
88            1 => Some(CoreldoVddLvl::Mid),
89            2 => Some(CoreldoVddLvl::Normal),
90            3 => Some(CoreldoVddLvl::Over),
91            _ => None,
92        }
93    }
94    #[doc = "Regulate to mid voltage (1.0 V)"]
95    #[inline(always)]
96    pub fn is_mid(&self) -> bool {
97        *self == CoreldoVddLvl::Mid
98    }
99    #[doc = "Regulate to normal voltage (1.1 V)"]
100    #[inline(always)]
101    pub fn is_normal(&self) -> bool {
102        *self == CoreldoVddLvl::Normal
103    }
104    #[doc = "Regulate to overdrive voltage (1.15 V)"]
105    #[inline(always)]
106    pub fn is_over(&self) -> bool {
107        *self == CoreldoVddLvl::Over
108    }
109}
110#[doc = "Field `CORELDO_VDD_LVL` writer - LDO_CORE VDD Regulator Voltage Level"]
111pub type CoreldoVddLvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, CoreldoVddLvl>;
112impl<'a, REG> CoreldoVddLvlW<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115    REG::Ux: From<u8>,
116{
117    #[doc = "Regulate to mid voltage (1.0 V)"]
118    #[inline(always)]
119    pub fn mid(self) -> &'a mut crate::W<REG> {
120        self.variant(CoreldoVddLvl::Mid)
121    }
122    #[doc = "Regulate to normal voltage (1.1 V)"]
123    #[inline(always)]
124    pub fn normal(self) -> &'a mut crate::W<REG> {
125        self.variant(CoreldoVddLvl::Normal)
126    }
127    #[doc = "Regulate to overdrive voltage (1.15 V)"]
128    #[inline(always)]
129    pub fn over(self) -> &'a mut crate::W<REG> {
130        self.variant(CoreldoVddLvl::Over)
131    }
132}
133#[doc = "Bandgap Mode\n\nValue on reset: 1"]
134#[cfg_attr(feature = "defmt", derive(defmt::Format))]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136#[repr(u8)]
137pub enum Bgmode {
138    #[doc = "0: Bandgap disabled"]
139    Bgmode0 = 0,
140    #[doc = "1: Bandgap enabled, buffer disabled"]
141    Bgmode01 = 1,
142    #[doc = "2: Bandgap enabled, buffer enabled"]
143    Bgmode10 = 2,
144}
145impl From<Bgmode> for u8 {
146    #[inline(always)]
147    fn from(variant: Bgmode) -> Self {
148        variant as _
149    }
150}
151impl crate::FieldSpec for Bgmode {
152    type Ux = u8;
153}
154impl crate::IsEnum for Bgmode {}
155#[doc = "Field `BGMODE` reader - Bandgap Mode"]
156pub type BgmodeR = crate::FieldReader<Bgmode>;
157impl BgmodeR {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<Bgmode> {
161        match self.bits {
162            0 => Some(Bgmode::Bgmode0),
163            1 => Some(Bgmode::Bgmode01),
164            2 => Some(Bgmode::Bgmode10),
165            _ => None,
166        }
167    }
168    #[doc = "Bandgap disabled"]
169    #[inline(always)]
170    pub fn is_bgmode0(&self) -> bool {
171        *self == Bgmode::Bgmode0
172    }
173    #[doc = "Bandgap enabled, buffer disabled"]
174    #[inline(always)]
175    pub fn is_bgmode01(&self) -> bool {
176        *self == Bgmode::Bgmode01
177    }
178    #[doc = "Bandgap enabled, buffer enabled"]
179    #[inline(always)]
180    pub fn is_bgmode10(&self) -> bool {
181        *self == Bgmode::Bgmode10
182    }
183}
184#[doc = "Field `BGMODE` writer - Bandgap Mode"]
185pub type BgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bgmode>;
186impl<'a, REG> BgmodeW<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189    REG::Ux: From<u8>,
190{
191    #[doc = "Bandgap disabled"]
192    #[inline(always)]
193    pub fn bgmode0(self) -> &'a mut crate::W<REG> {
194        self.variant(Bgmode::Bgmode0)
195    }
196    #[doc = "Bandgap enabled, buffer disabled"]
197    #[inline(always)]
198    pub fn bgmode01(self) -> &'a mut crate::W<REG> {
199        self.variant(Bgmode::Bgmode01)
200    }
201    #[doc = "Bandgap enabled, buffer enabled"]
202    #[inline(always)]
203    pub fn bgmode10(self) -> &'a mut crate::W<REG> {
204        self.variant(Bgmode::Bgmode10)
205    }
206}
207#[doc = "VDD Voltage Detect Disable\n\nValue on reset: 0"]
208#[cfg_attr(feature = "defmt", derive(defmt::Format))]
209#[derive(Clone, Copy, Debug, PartialEq, Eq)]
210pub enum VddVdDisable {
211    #[doc = "0: Enable"]
212    Enable = 0,
213    #[doc = "1: Disable"]
214    Disable = 1,
215}
216impl From<VddVdDisable> for bool {
217    #[inline(always)]
218    fn from(variant: VddVdDisable) -> Self {
219        variant as u8 != 0
220    }
221}
222#[doc = "Field `VDD_VD_DISABLE` reader - VDD Voltage Detect Disable"]
223pub type VddVdDisableR = crate::BitReader<VddVdDisable>;
224impl VddVdDisableR {
225    #[doc = "Get enumerated values variant"]
226    #[inline(always)]
227    pub const fn variant(&self) -> VddVdDisable {
228        match self.bits {
229            false => VddVdDisable::Enable,
230            true => VddVdDisable::Disable,
231        }
232    }
233    #[doc = "Enable"]
234    #[inline(always)]
235    pub fn is_enable(&self) -> bool {
236        *self == VddVdDisable::Enable
237    }
238    #[doc = "Disable"]
239    #[inline(always)]
240    pub fn is_disable(&self) -> bool {
241        *self == VddVdDisable::Disable
242    }
243}
244#[doc = "Field `VDD_VD_DISABLE` writer - VDD Voltage Detect Disable"]
245pub type VddVdDisableW<'a, REG> = crate::BitWriter<'a, REG, VddVdDisable>;
246impl<'a, REG> VddVdDisableW<'a, REG>
247where
248    REG: crate::Writable + crate::RegisterSpec,
249{
250    #[doc = "Enable"]
251    #[inline(always)]
252    pub fn enable(self) -> &'a mut crate::W<REG> {
253        self.variant(VddVdDisable::Enable)
254    }
255    #[doc = "Disable"]
256    #[inline(always)]
257    pub fn disable(self) -> &'a mut crate::W<REG> {
258        self.variant(VddVdDisable::Disable)
259    }
260}
261#[doc = "Core Low-Voltage Detection Enable\n\nValue on reset: 1"]
262#[cfg_attr(feature = "defmt", derive(defmt::Format))]
263#[derive(Clone, Copy, Debug, PartialEq, Eq)]
264pub enum CoreLvde {
265    #[doc = "0: Disable"]
266    Disable = 0,
267    #[doc = "1: Enable"]
268    Enable = 1,
269}
270impl From<CoreLvde> for bool {
271    #[inline(always)]
272    fn from(variant: CoreLvde) -> Self {
273        variant as u8 != 0
274    }
275}
276#[doc = "Field `CORE_LVDE` reader - Core Low-Voltage Detection Enable"]
277pub type CoreLvdeR = crate::BitReader<CoreLvde>;
278impl CoreLvdeR {
279    #[doc = "Get enumerated values variant"]
280    #[inline(always)]
281    pub const fn variant(&self) -> CoreLvde {
282        match self.bits {
283            false => CoreLvde::Disable,
284            true => CoreLvde::Enable,
285        }
286    }
287    #[doc = "Disable"]
288    #[inline(always)]
289    pub fn is_disable(&self) -> bool {
290        *self == CoreLvde::Disable
291    }
292    #[doc = "Enable"]
293    #[inline(always)]
294    pub fn is_enable(&self) -> bool {
295        *self == CoreLvde::Enable
296    }
297}
298#[doc = "Field `CORE_LVDE` writer - Core Low-Voltage Detection Enable"]
299pub type CoreLvdeW<'a, REG> = crate::BitWriter<'a, REG, CoreLvde>;
300impl<'a, REG> CoreLvdeW<'a, REG>
301where
302    REG: crate::Writable + crate::RegisterSpec,
303{
304    #[doc = "Disable"]
305    #[inline(always)]
306    pub fn disable(self) -> &'a mut crate::W<REG> {
307        self.variant(CoreLvde::Disable)
308    }
309    #[doc = "Enable"]
310    #[inline(always)]
311    pub fn enable(self) -> &'a mut crate::W<REG> {
312        self.variant(CoreLvde::Enable)
313    }
314}
315#[doc = "System Low-Voltage Detection Enable\n\nValue on reset: 1"]
316#[cfg_attr(feature = "defmt", derive(defmt::Format))]
317#[derive(Clone, Copy, Debug, PartialEq, Eq)]
318pub enum SysLvde {
319    #[doc = "0: Disable"]
320    Disable = 0,
321    #[doc = "1: Enable"]
322    Enable = 1,
323}
324impl From<SysLvde> for bool {
325    #[inline(always)]
326    fn from(variant: SysLvde) -> Self {
327        variant as u8 != 0
328    }
329}
330#[doc = "Field `SYS_LVDE` reader - System Low-Voltage Detection Enable"]
331pub type SysLvdeR = crate::BitReader<SysLvde>;
332impl SysLvdeR {
333    #[doc = "Get enumerated values variant"]
334    #[inline(always)]
335    pub const fn variant(&self) -> SysLvde {
336        match self.bits {
337            false => SysLvde::Disable,
338            true => SysLvde::Enable,
339        }
340    }
341    #[doc = "Disable"]
342    #[inline(always)]
343    pub fn is_disable(&self) -> bool {
344        *self == SysLvde::Disable
345    }
346    #[doc = "Enable"]
347    #[inline(always)]
348    pub fn is_enable(&self) -> bool {
349        *self == SysLvde::Enable
350    }
351}
352#[doc = "Field `SYS_LVDE` writer - System Low-Voltage Detection Enable"]
353pub type SysLvdeW<'a, REG> = crate::BitWriter<'a, REG, SysLvde>;
354impl<'a, REG> SysLvdeW<'a, REG>
355where
356    REG: crate::Writable + crate::RegisterSpec,
357{
358    #[doc = "Disable"]
359    #[inline(always)]
360    pub fn disable(self) -> &'a mut crate::W<REG> {
361        self.variant(SysLvde::Disable)
362    }
363    #[doc = "Enable"]
364    #[inline(always)]
365    pub fn enable(self) -> &'a mut crate::W<REG> {
366        self.variant(SysLvde::Enable)
367    }
368}
369#[doc = "System High-Voltage Detection Enable\n\nValue on reset: 1"]
370#[cfg_attr(feature = "defmt", derive(defmt::Format))]
371#[derive(Clone, Copy, Debug, PartialEq, Eq)]
372pub enum SysHvde {
373    #[doc = "0: Disable"]
374    Disable = 0,
375    #[doc = "1: Enable"]
376    Enable = 1,
377}
378impl From<SysHvde> for bool {
379    #[inline(always)]
380    fn from(variant: SysHvde) -> Self {
381        variant as u8 != 0
382    }
383}
384#[doc = "Field `SYS_HVDE` reader - System High-Voltage Detection Enable"]
385pub type SysHvdeR = crate::BitReader<SysHvde>;
386impl SysHvdeR {
387    #[doc = "Get enumerated values variant"]
388    #[inline(always)]
389    pub const fn variant(&self) -> SysHvde {
390        match self.bits {
391            false => SysHvde::Disable,
392            true => SysHvde::Enable,
393        }
394    }
395    #[doc = "Disable"]
396    #[inline(always)]
397    pub fn is_disable(&self) -> bool {
398        *self == SysHvde::Disable
399    }
400    #[doc = "Enable"]
401    #[inline(always)]
402    pub fn is_enable(&self) -> bool {
403        *self == SysHvde::Enable
404    }
405}
406#[doc = "Field `SYS_HVDE` writer - System High-Voltage Detection Enable"]
407pub type SysHvdeW<'a, REG> = crate::BitWriter<'a, REG, SysHvde>;
408impl<'a, REG> SysHvdeW<'a, REG>
409where
410    REG: crate::Writable + crate::RegisterSpec,
411{
412    #[doc = "Disable"]
413    #[inline(always)]
414    pub fn disable(self) -> &'a mut crate::W<REG> {
415        self.variant(SysHvde::Disable)
416    }
417    #[doc = "Enable"]
418    #[inline(always)]
419    pub fn enable(self) -> &'a mut crate::W<REG> {
420        self.variant(SysHvde::Enable)
421    }
422}
423impl R {
424    #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"]
425    #[inline(always)]
426    pub fn coreldo_vdd_ds(&self) -> CoreldoVddDsR {
427        CoreldoVddDsR::new((self.bits & 1) != 0)
428    }
429    #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"]
430    #[inline(always)]
431    pub fn coreldo_vdd_lvl(&self) -> CoreldoVddLvlR {
432        CoreldoVddLvlR::new(((self.bits >> 2) & 3) as u8)
433    }
434    #[doc = "Bits 20:21 - Bandgap Mode"]
435    #[inline(always)]
436    pub fn bgmode(&self) -> BgmodeR {
437        BgmodeR::new(((self.bits >> 20) & 3) as u8)
438    }
439    #[doc = "Bit 23 - VDD Voltage Detect Disable"]
440    #[inline(always)]
441    pub fn vdd_vd_disable(&self) -> VddVdDisableR {
442        VddVdDisableR::new(((self.bits >> 23) & 1) != 0)
443    }
444    #[doc = "Bit 24 - Core Low-Voltage Detection Enable"]
445    #[inline(always)]
446    pub fn core_lvde(&self) -> CoreLvdeR {
447        CoreLvdeR::new(((self.bits >> 24) & 1) != 0)
448    }
449    #[doc = "Bit 25 - System Low-Voltage Detection Enable"]
450    #[inline(always)]
451    pub fn sys_lvde(&self) -> SysLvdeR {
452        SysLvdeR::new(((self.bits >> 25) & 1) != 0)
453    }
454    #[doc = "Bit 28 - System High-Voltage Detection Enable"]
455    #[inline(always)]
456    pub fn sys_hvde(&self) -> SysHvdeR {
457        SysHvdeR::new(((self.bits >> 28) & 1) != 0)
458    }
459}
460#[cfg(feature = "debug")]
461impl core::fmt::Debug for R {
462    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
463        f.debug_struct("ACTIVE_CFG")
464            .field("coreldo_vdd_ds", &self.coreldo_vdd_ds())
465            .field("coreldo_vdd_lvl", &self.coreldo_vdd_lvl())
466            .field("bgmode", &self.bgmode())
467            .field("vdd_vd_disable", &self.vdd_vd_disable())
468            .field("core_lvde", &self.core_lvde())
469            .field("sys_lvde", &self.sys_lvde())
470            .field("sys_hvde", &self.sys_hvde())
471            .finish()
472    }
473}
474impl W {
475    #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"]
476    #[inline(always)]
477    pub fn coreldo_vdd_ds(&mut self) -> CoreldoVddDsW<'_, ActiveCfgSpec> {
478        CoreldoVddDsW::new(self, 0)
479    }
480    #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"]
481    #[inline(always)]
482    pub fn coreldo_vdd_lvl(&mut self) -> CoreldoVddLvlW<'_, ActiveCfgSpec> {
483        CoreldoVddLvlW::new(self, 2)
484    }
485    #[doc = "Bits 20:21 - Bandgap Mode"]
486    #[inline(always)]
487    pub fn bgmode(&mut self) -> BgmodeW<'_, ActiveCfgSpec> {
488        BgmodeW::new(self, 20)
489    }
490    #[doc = "Bit 23 - VDD Voltage Detect Disable"]
491    #[inline(always)]
492    pub fn vdd_vd_disable(&mut self) -> VddVdDisableW<'_, ActiveCfgSpec> {
493        VddVdDisableW::new(self, 23)
494    }
495    #[doc = "Bit 24 - Core Low-Voltage Detection Enable"]
496    #[inline(always)]
497    pub fn core_lvde(&mut self) -> CoreLvdeW<'_, ActiveCfgSpec> {
498        CoreLvdeW::new(self, 24)
499    }
500    #[doc = "Bit 25 - System Low-Voltage Detection Enable"]
501    #[inline(always)]
502    pub fn sys_lvde(&mut self) -> SysLvdeW<'_, ActiveCfgSpec> {
503        SysLvdeW::new(self, 25)
504    }
505    #[doc = "Bit 28 - System High-Voltage Detection Enable"]
506    #[inline(always)]
507    pub fn sys_hvde(&mut self) -> SysHvdeW<'_, ActiveCfgSpec> {
508        SysHvdeW::new(self, 28)
509    }
510}
511#[doc = "Active Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
512pub struct ActiveCfgSpec;
513impl crate::RegisterSpec for ActiveCfgSpec {
514    type Ux = u32;
515}
516#[doc = "`read()` method returns [`active_cfg::R`](R) reader structure"]
517impl crate::Readable for ActiveCfgSpec {}
518#[doc = "`write(|w| ..)` method takes [`active_cfg::W`](W) writer structure"]
519impl crate::Writable for ActiveCfgSpec {
520    type Safety = crate::Unsafe;
521}
522#[doc = "`reset()` method sets ACTIVE_CFG to value 0x1310_0005"]
523impl crate::Resettable for ActiveCfgSpec {
524    const RESET_VALUE: u32 = 0x1310_0005;
525}
mcxa_pac/spc0/active_cfg.rs

mcxa_pac/spc0/
active_cfg.rs
