mcxa_pac/smartdma0/
break_addr.rs1#[doc = "Register `BREAK_ADDR` reader"]
2pub type R = crate::R<BreakAddrSpec>;
3#[doc = "Register `BREAK_ADDR` writer"]
4pub type W = crate::W<BreakAddrSpec>;
5#[doc = "Field `ADDR` reader - 32-bit address to swap to EZHB_BREAK_VECT location"]
6pub type AddrR = crate::FieldReader<u32>;
7#[doc = "Field `ADDR` writer - 32-bit address to swap to EZHB_BREAK_VECT location"]
8pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
9impl R {
10 #[doc = "Bits 2:31 - 32-bit address to swap to EZHB_BREAK_VECT location"]
11 #[inline(always)]
12 pub fn addr(&self) -> AddrR {
13 AddrR::new((self.bits >> 2) & 0x3fff_ffff)
14 }
15}
16#[cfg(feature = "debug")]
17impl core::fmt::Debug for R {
18 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19 f.debug_struct("BREAK_ADDR").field("addr", &self.addr()).finish()
20 }
21}
22impl W {
23 #[doc = "Bits 2:31 - 32-bit address to swap to EZHB_BREAK_VECT location"]
24 #[inline(always)]
25 pub fn addr(&mut self) -> AddrW<'_, BreakAddrSpec> {
26 AddrW::new(self, 2)
27 }
28}
29#[doc = "Breakpoint Address\n\nYou can [`read`](crate::Reg::read) this register and get [`break_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct BreakAddrSpec;
31impl crate::RegisterSpec for BreakAddrSpec {
32 type Ux = u32;
33}
34#[doc = "`read()` method returns [`break_addr::R`](R) reader structure"]
35impl crate::Readable for BreakAddrSpec {}
36#[doc = "`write(|w| ..)` method takes [`break_addr::W`](W) writer structure"]
37impl crate::Writable for BreakAddrSpec {
38 type Safety = crate::Unsafe;
39}
40#[doc = "`reset()` method sets BREAK_ADDR to value 0"]
41impl crate::Resettable for BreakAddrSpec {}