mcxa_pac/sgi0/
sgi_int_enable.rs

1#[doc = "Register `sgi_int_enable` reader"]
2pub type R = crate::R<SgiIntEnableSpec>;
3#[doc = "Register `sgi_int_enable` writer"]
4pub type W = crate::W<SgiIntEnableSpec>;
5#[doc = "Field `int_en` reader - Interrupt enable bit"]
6pub type IntEnR = crate::BitReader;
7#[doc = "Field `int_en` writer - Interrupt enable bit"]
8pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `int_ena_rsvd` reader - reserved"]
10pub type IntEnaRsvdR = crate::FieldReader<u32>;
11impl R {
12    #[doc = "Bit 0 - Interrupt enable bit"]
13    #[inline(always)]
14    pub fn int_en(&self) -> IntEnR {
15        IntEnR::new((self.bits & 1) != 0)
16    }
17    #[doc = "Bits 1:31 - reserved"]
18    #[inline(always)]
19    pub fn int_ena_rsvd(&self) -> IntEnaRsvdR {
20        IntEnaRsvdR::new((self.bits >> 1) & 0x7fff_ffff)
21    }
22}
23#[cfg(feature = "debug")]
24impl core::fmt::Debug for R {
25    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
26        f.debug_struct("sgi_int_enable")
27            .field("int_en", &self.int_en())
28            .field("int_ena_rsvd", &self.int_ena_rsvd())
29            .finish()
30    }
31}
32impl W {
33    #[doc = "Bit 0 - Interrupt enable bit"]
34    #[inline(always)]
35    pub fn int_en(&mut self) -> IntEnW<'_, SgiIntEnableSpec> {
36        IntEnW::new(self, 0)
37    }
38}
39#[doc = "Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
40pub struct SgiIntEnableSpec;
41impl crate::RegisterSpec for SgiIntEnableSpec {
42    type Ux = u32;
43}
44#[doc = "`read()` method returns [`sgi_int_enable::R`](R) reader structure"]
45impl crate::Readable for SgiIntEnableSpec {}
46#[doc = "`write(|w| ..)` method takes [`sgi_int_enable::W`](W) writer structure"]
47impl crate::Writable for SgiIntEnableSpec {
48    type Safety = crate::Unsafe;
49}
50#[doc = "`reset()` method sets sgi_int_enable to value 0"]
51impl crate::Resettable for SgiIntEnableSpec {}
mcxa_pac/sgi0/sgi_int_enable.rs

mcxa_pac/sgi0/
sgi_int_enable.rs
